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Searched refs:PCIE (Results 1 – 25 of 26) sorted by relevance

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/rk3399_rockchip-uboot/doc/
H A DREADME.srio-pcie-boot-corenet2 SRIO and PCIE Boot on Corenet Platforms
5 For some PowerPC processors with SRIO or PCIE interface, boot location can be
6 configured to SRIO or PCIE by RCW. The processor booting from SRIO or PCIE can
8 from another processor's memory space by SRIO or PCIE link connected between
12 platforms and a RCW example with boot from SRIO or PCIE configuration.
14 Environment of the SRIO or PCIE boot:
16 b) They are connected with SRIO or PCIE links, whether 1x, 2x or 4x, and
21 e) Slave's RCW should configure the SerDes for SRIO or PCIE boot port, set
22 the boot location to SRIO or PCIE, and holdoff all the cores.
27 | NorFlash|<----->| Master |SRIO or PCIE | Slave |<---->[EEPROM]
[all …]
/rk3399_rockchip-uboot/drivers/phy/marvell/
H A Dcomphy_a3700.c144 reg_set16((void __iomem *)LANE_CFG1_ADDR(PCIE), in comphy_pcie_power_up()
150 reg_set16((void __iomem *)GLOB_CLK_SRC_LO_ADDR(PCIE), in comphy_pcie_power_up()
156 reg_set16((void __iomem *)MISC_REG1_ADDR(PCIE), in comphy_pcie_power_up()
162 reg_set16((void __iomem *)PWR_MGM_TIM1_ADDR(PCIE), 0x10C, 0xFFFF); in comphy_pcie_power_up()
167 reg_set16((void __iomem *)UNIT_CTRL_ADDR(PCIE), in comphy_pcie_power_up()
173 reg_set16((void __iomem *)MISC_REG0_ADDR(PCIE), in comphy_pcie_power_up()
186 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), in comphy_pcie_power_up()
189 reg_set16((void __iomem *)PWR_PLL_CTRL_ADDR(PCIE), in comphy_pcie_power_up()
196 reg_set16((void __iomem *)KVCO_CAL_CTRL_ADDR(PCIE), in comphy_pcie_power_up()
203 reg_set16((void __iomem *)SYNC_PATTERN_ADDR(PCIE), in comphy_pcie_power_up()
[all …]
H A Dcomphy_a3700.h71 #define PCIE 1 macro
74 #define PHY_BASE(unit) ((unit == PCIE) ? PCIEPHY_BASE : USB3PHY_BASE)
75 #define PHY_SHFT(unit) ((unit == PCIE) ? PCIEPHY_SHFT : USB3PHY_SHFT)
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra30/
H A Dpinmux.c264 PIN(PEX_L0_PRSNT_N_PDD0, PCIE, HDA, RSVD3, RSVD4),
265 PIN(PEX_L0_RST_N_PDD1, PCIE, HDA, RSVD3, RSVD4),
266 PIN(PEX_L0_CLKREQ_N_PDD2, PCIE, HDA, RSVD3, RSVD4),
267 PIN(PEX_WAKE_N_PDD3, PCIE, HDA, RSVD3, RSVD4),
268 PIN(PEX_L1_PRSNT_N_PDD4, PCIE, HDA, RSVD3, RSVD4),
269 PIN(PEX_L1_RST_N_PDD5, PCIE, HDA, RSVD3, RSVD4),
270 PIN(PEX_L1_CLKREQ_N_PDD6, PCIE, HDA, RSVD3, RSVD4),
271 PIN(PEX_L2_PRSNT_N_PDD7, PCIE, HDA, RSVD3, RSVD4),
272 PIN(PEX_L2_RST_N_PCC6, PCIE, HDA, RSVD3, RSVD4),
273 PIN(PEX_L2_CLKREQ_N_PCC7, PCIE, HDA, RSVD3, RSVD4),
H A Dclock.c314 NONE(PCIE),
/rk3399_rockchip-uboot/board/avionic-design/common/
H A Dpinmux-config-tamonten-ng.h264 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
265 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
266 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
267 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
268 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
269 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
270 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
272 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
273 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/rk3399_rockchip-uboot/board/nvidia/cardhu/
H A Dpinmux-config-cardhu.h268 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
269 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
270 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
271 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
272 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
273 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
274 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
275 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
276 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
277 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/rk3399_rockchip-uboot/board/toradex/apalis_t30/
H A Dpinmux-config-apalis_t30.h288 DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT),
289 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
290 DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT),
291 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
293 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
294 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
295 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, DOWN, TRISTATE, OUTPUT), /* NC */
296 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
297 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
298 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/rk3399_rockchip-uboot/configs/
H A Dsbc8548_PCI_33_PCIE_defconfig7 CONFIG_SYS_EXTRA_OPTIONS="33,PCIE"
H A Dsbc8548_PCI_66_PCIE_defconfig7 CONFIG_SYS_EXTRA_OPTIONS="66,PCIE"
/rk3399_rockchip-uboot/board/freescale/p1_p2_rdb_pc/
H A DREADME23 * PCIE slot and mini-PCIE slots
/rk3399_rockchip-uboot/board/toradex/colibri_t30/
H A Dpinmux-config-colibri_t30.h280 DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT),
285 DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT),
286 DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT),
287 DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT),
288 DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT),
289 DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT),
290 DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT),
291 DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT),
/rk3399_rockchip-uboot/board/freescale/c29xpcie/
H A DREADME34 0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory
37 0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dzynqmp-zcu102-revA.dts171 output-high; /* PCIE = 0, DP = 1 */
177 output-high; /* PCIE = 0, DP = 1 */
183 output-high; /* PCIE = 0, USB0 = 1 */
189 output-high; /* PCIE = 0, SATA = 1 */
H A Dam57xx-idk-common.dtsi175 /* R1.3a 572x V1_8PHY_LDO4: PCIE, HDMI*/
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra20/
H A Dpinmux.c305 PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
326 PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
329 PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
H A Dclock.c332 NONE(PCIE),
/rk3399_rockchip-uboot/board/freescale/t4qds/
H A DREADME107 0x0_8000_0000 (0xc_0000_0000) - 0x0_dfff_ffff 1.5GB PCIE memory
111 0x0_f800_0000 (0xf_f800_0000) - 0x0_f803_ffff 256KB PCIE IO
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra114/
H A Dclock.c314 NONE(PCIE),
/rk3399_rockchip-uboot/board/hisilicon/poplar/
H A DREADME18 PCIE One PCIe 2.0 interfaces
/rk3399_rockchip-uboot/board/freescale/t208xqds/
H A DREADME72 PCIE:
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra124/
H A Dclock.c414 NONE(PCIE),
/rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/
H A Dclock.c445 NONE(PCIE),
/rk3399_rockchip-uboot/env/
H A DKconfig291 space by SRIO or PCIE links.
/rk3399_rockchip-uboot/common/spl/
H A DKconfig621 bool "Support loading from PCIE EP"
623 Enable support for PCIE EP driver in SPL. The RC will download the

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