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Searched refs:MII_BMCR (Results 1 – 25 of 42) sorted by relevance

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/rk3399_rockchip-uboot/drivers/net/phy/
H A Daquantia.c24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
32 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
40 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
56 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
95 speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_startup()
H A Dxilinx_phy.c72 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
121 temp = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_config()
123 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, temp); in xilinxphy_config()
H A Det1011c.c31 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
37 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
H A Dphy.c143 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_setup_forced()
157 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_restart_aneg()
167 ctl = phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl); in genphy_restart_aneg()
196 int ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_config_aneg()
364 u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in genphy_parse_link()
796 if (phy_write(phydev, devad, MII_BMCR, BMCR_RESET) < 0) { in phy_reset()
809 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
811 reg = phy_read(phydev, devad, MII_BMCR); in phy_reset()
H A Dnatsemi.c22 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
58 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
H A Dmarvell.c111 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
119 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in m88e1011s_config()
486 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1145_config()
488 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1145_config()
587 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in m88e1680_config()
589 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in m88e1680_config()
H A Dmscc.c253 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
254 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, (reg_val | BMCR_RESET)); in mscc_phy_soft_reset()
256 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
259 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in mscc_phy_soft_reset()
H A Ddavicom.c29 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
H A Drealtek.c66 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211f_config()
H A Dbroadcom.c138 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in bcm5482_config()
140 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); in bcm5482_config()
H A Dmicrel_ksz90x1.c357 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in ksz9031_config()
359 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, bmcr); in ksz9031_config()
H A Dmv88e61xx.c572 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR); in mv88e61xx_serdes_init()
576 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val); in mv88e61xx_serdes_init()
782 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR); in mv88e61xx_phy_enable()
786 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val); in mv88e61xx_phy_enable()
/rk3399_rockchip-uboot/drivers/qe/
H A Duec_phy.c260 ctrl = uec_phy_read(mii_info, MII_BMCR); in genmii_setup_forced()
290 uec_phy_write(mii_info, MII_BMCR, ctrl); in genmii_setup_forced()
298 ctl = uec_phy_read(mii_info, MII_BMCR); in genmii_restart_aneg()
300 uec_phy_write(mii_info, MII_BMCR, ctl); in genmii_restart_aneg()
335 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in marvell_config_aneg()
512 uec_phy_write(mii_info, MII_BMCR, BMCR_RESET); in uec_marvell_init()
584 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) | in dm9161_init()
587 uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) & in dm9161_init()
900 status = uec_phy_read(mii_info, MII_BMCR); in marvell_phy_interface_mode()
901 uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE); in marvell_phy_interface_mode()
/rk3399_rockchip-uboot/arch/arm/mach-davinci/
H A Dlxt972.c93 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in lxt972_auto_negotiate()
98 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); in lxt972_auto_negotiate()
/rk3399_rockchip-uboot/common/
H A Dmiiphyutil.c355 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
359 if (miiphy_write(devname, addr, MII_BMCR, reg | BMCR_RESET) != 0) { in miiphy_reset()
373 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
421 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_speed()
484 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_duplex()
/rk3399_rockchip-uboot/cmd/
H A Dmii.c22 { MII_BMCR, "PHY control register" },
199 if ((regno == MII_BMCR) && (pdesc->lo == 6)) { in special_field()
211 else if ((regno == MII_BMCR) && (pdesc->lo == 8)) { in special_field()
/rk3399_rockchip-uboot/board/egnite/ethernut5/
H A Dethernut5.c175 miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); in board_eth_init()
/rk3399_rockchip-uboot/board/aries/m28evk/
H A Dm28evk.c104 miiphy_write("FEC1", phy, MII_BMCR, 0x9000); in fecmxc_mii_postcall()
/rk3399_rockchip-uboot/test/rockchip/
H A Dtest-net.c108 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in eth_setup_loopback_test()
122 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, val); in eth_setup_loopback_test()
/rk3399_rockchip-uboot/drivers/net/
H A Dsmc911x.c88 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_RESET); in smc911x_phy_configure()
91 smc911x_eth_phy_write(dev, 1, MII_BMCR, BMCR_ANENABLE | in smc911x_phy_configure()
H A Ddavinci_emac.c327 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in gen_auto_negotiate()
332 davinci_eth_phy_write(phy_addr, MII_BMCR, val); in gen_auto_negotiate()
341 if (!davinci_eth_phy_read(phy_addr, MII_BMCR, &tmp)) in gen_auto_negotiate()
354 davinci_eth_phy_write(phy_addr, MII_BMCR, tmp); in gen_auto_negotiate()
H A Dax88180.c116 ax88180_mdio_write (dev, MII_BMCR, (BMCR_RESET | BMCR_ANENABLE)); in ax88180_phy_reset()
119 while (ax88180_mdio_read (dev, MII_BMCR) & BMCR_RESET) { in ax88180_phy_reset()
351 bmcr_val = ax88180_mdio_read (dev, MII_BMCR); in ax88180_media_config()
/rk3399_rockchip-uboot/include/linux/
H A Dmii.h13 #define MII_BMCR 0x00 /* Basic mode control register */ macro
H A Dmdio.h29 #define MDIO_CTRL1 MII_BMCR
/rk3399_rockchip-uboot/drivers/usb/eth/
H A Dmcs7830.c323 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
327 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()
331 rc = mcs7830_write_phy(udev, MII_BMCR, flg); in mcs7830_set_autoneg()

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