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Searched refs:M4 (Results 1 – 25 of 34) sorted by relevance

12

/rk3399_rockchip-uboot/board/htkw/mcx/
H A Dmcx.h78 MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
79 MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
80 MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
81 MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
82 MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
83 MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
84 MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
85 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
86 MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
87 MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
[all …]
/rk3399_rockchip-uboot/board/overo/
H A Dovero.h45 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
47 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
49 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
80 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*CAM_FLD*/\
84 MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\
87 MUX_VAL(CP(UART2_CTS), (IEN | PTD | DIS | M4)) /*GPIO_144 - LCD_EN*/\
88 MUX_VAL(CP(UART2_RTS), (IEN | PTD | DIS | M4)) /*GPIO_145*/\
89 MUX_VAL(CP(UART2_TX), (IEN | PTD | DIS | M4)) /*GPIO_146*/\
90 MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M4)) /*GPIO_147*/\
92 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
[all …]
H A Dcommon.c110 MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /*GPIO_54*/\
138 MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) /*GPIO_112*/\
139 MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) /*GPIO_113*/\
140 MUX_VAL(CP(CSI2_DY1), (IEN | PTD | EN | M4)) /*GPIO_115*/\
158 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
167 MUX_VAL(CP(MMC2_DAT7), (IEN | PTU | EN | M4)) /*GPIO_139*/\
173 MUX_VAL(CP(UART1_RTS), (IEN | PTU | DIS | M4)) /*GPIO_149*/ \
186 MUX_VAL(CP(UART3_RTS_SD), (IEN | PTU | EN | M4)) /*GPIO_164 W2W_*/\
204 MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M4)) /*GPIO_168*/\
206 MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M4)) /*GPIO_183*/\
[all …]
/rk3399_rockchip-uboot/board/teejet/mt_ventoux/
H A Dmt_ventoux.h116 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTD | EN | M4))/* GPIO 53 */\
117 MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) /* GPIO 54 */\
118 MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
120 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M4)) \
122 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
129 MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M4)) \
131 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M4)) \
132 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
133 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
135 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
[all …]
H A Dmt_ventoux.c233 MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) in board_init()
235 MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) in board_init()
/rk3399_rockchip-uboot/board/ti/panda/
H A Dpanda_mux_data.h50 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
51 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
52 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
53 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
54 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
55 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
56 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
57 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
58 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
59 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
[all …]
/rk3399_rockchip-uboot/board/pandora/
H A Dpandora.h132 MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | DIS | M4)) /*GPIO_96 - LEFT*/\
133 MUX_VAL(CP(CAM_PCLK), (IEN | PTD | DIS | M4)) /*GPIO_97 - L2*/\
134 MUX_VAL(CP(CAM_FLD), (IEN | PTD | DIS | M4)) /*GPIO_98 - RIGHT*/\
135 MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*GPIO_99 - MENU*/\
136 MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*GPIO_100 - START*/\
137 MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M4)) /*GPIO_101 - Y*/\
138 MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M4)) /*GPIO_102 - L1*/\
139 MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M4)) /*GPIO_103 - DOWN*/\
140 MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M4)) /*GPIO_104 - SELECT*/\
141 MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*GPIO_105 - R1*/\
[all …]
/rk3399_rockchip-uboot/board/corscience/tricorder/
H A Dtricorder.h78 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
79 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
149 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
163 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
186 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
187 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
188 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
189 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
190 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
191 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
[all …]
/rk3399_rockchip-uboot/board/lg/sniper/
H A Dsniper.h54 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M4)) /* gpio_34 */ \
55 MUX_VAL(CP(GPMC_A2), (IEN | PTD | DIS | M4)) /* gpio_35 */ \
56 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M4)) /* gpio_36 */ \
57 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M4)) /* gpio_37 */\
58 MUX_VAL(CP(GPMC_A5), (IEN | PTD | DIS | M4)) /* gpio_38 */\
59 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M4)) /* gpio_39 */\
60 MUX_VAL(CP(GPMC_A7), (IEN | PTD | DIS | M4)) /* gpio_40 */\
61 MUX_VAL(CP(GPMC_A8), (IEN | PTD | DIS | M4)) /* gpio_41 */\
62 MUX_VAL(CP(GPMC_A9), (IEN | PTD | EN | M4)) /* gpio_42 */\
63 MUX_VAL(CP(GPMC_A10), (IEN | PTD | DIS | M4)) /* gpio_43 */\
[all …]
/rk3399_rockchip-uboot/board/technexion/twister/
H A Dtwister.h122 MUX_VAL(CP(GPMC_NCS4), (IEN | PTD | EN | M4)) \
125 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTD | EN | M4)) /*GPIO_58*/ \
134 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) \
135 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
136 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) \
171 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
185 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
198 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
200 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \
201 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
[all …]
/rk3399_rockchip-uboot/board/ti/beagle/
H A Dbeagle.h158 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
172 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
195 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
196 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
197 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
198 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
199 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
200 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
201 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
202 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
[all …]
/rk3399_rockchip-uboot/board/timll/devkit8000/
H A Ddevkit8000.h152 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
166 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
189 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
190 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
191 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
192 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
193 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
194 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
195 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
196 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
[all …]
/rk3399_rockchip-uboot/board/8dtech/eco5pk/
H A Deco5pk.h113 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | DIS | M4)) \
123 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) \
131 MUX_VAL(CP(DSS_DATA0), (IEN | PTD | DIS | M4)) \
132 MUX_VAL(CP(DSS_DATA1), (IEN | PTD | DIS | M4)) \
133 MUX_VAL(CP(DSS_DATA2), (IEN | PTD | DIS | M4)) \
134 MUX_VAL(CP(DSS_DATA3), (IEN | PTD | DIS | M4)) \
135 MUX_VAL(CP(DSS_DATA4), (IEN | PTD | DIS | M4)) \
136 MUX_VAL(CP(DSS_DATA5), (IEN | PTD | DIS | M4)) \
137 MUX_VAL(CP(DSS_DATA6), (IEN | PTD | DIS | M4)) \
138 MUX_VAL(CP(DSS_DATA7), (IEN | PTD | DIS | M4)) \
[all …]
/rk3399_rockchip-uboot/board/nokia/rx51/
H A Drx51.h154 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
168 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
191 MUX_VAL(CP(MMC2_CLK), (IEN | PTU | EN | M4)) /*GPIO_130*/\
192 MUX_VAL(CP(MMC2_CMD), (IEN | PTU | EN | M4)) /*GPIO_131*/\
193 MUX_VAL(CP(MMC2_DAT0), (IEN | PTU | EN | M4)) /*GPIO_132*/\
194 MUX_VAL(CP(MMC2_DAT1), (IEN | PTU | EN | M4)) /*GPIO_133*/\
195 MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) /*GPIO_134*/\
196 MUX_VAL(CP(MMC2_DAT3), (IEN | PTU | EN | M4)) /*GPIO_135*/\
197 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) /*GPIO_136*/\
198 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) /*GPIO_137*/\
[all …]
/rk3399_rockchip-uboot/board/compulab/cm_t3517/
H A Dmux.c89 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/ in set_muxconf_regs()
91 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/ in set_muxconf_regs()
94 MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/ in set_muxconf_regs()
100 MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/ in set_muxconf_regs()
104 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/ in set_muxconf_regs()
110 MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/ in set_muxconf_regs()
112 MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/ in set_muxconf_regs()
115 MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/ in set_muxconf_regs()
117 MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/ in set_muxconf_regs()
119 MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/ in set_muxconf_regs()
[all …]
/rk3399_rockchip-uboot/board/gumstix/duovero/
H A Dduovero_mux_data.h100 {USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
101 {USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)}, /* usbb1_ulpiphy_stp */
102 {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dir */
103 {USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_nxt */
104 {USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat0 */
105 {USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat1 */
106 {USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat2 */
107 {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat3 */
108 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
109 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
[all …]
/rk3399_rockchip-uboot/board/isee/igep00x0/
H A Digep00x0.h115 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /* GPIO_2 */\
116 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /* GPIO_3 */\
117 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /* GPIO_4 */\
118 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /* GPIO_5 */\
119 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
120 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
121 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
122 MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
123 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
124 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
[all …]
/rk3399_rockchip-uboot/board/quipos/cairo/
H A Dcairo.h37 MUX_VAL(CONTROL_PADCONF_CAM_D0, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
38 MUX_VAL(CONTROL_PADCONF_CAM_D1, (IEN | DIS | SB_HIZ | M4)) \
40 MUX_VAL(CONTROL_PADCONF_CAM_D3, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
41 MUX_VAL(CONTROL_PADCONF_CAM_D4, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
46 MUX_VAL(CONTROL_PADCONF_CAM_D9, (IEN | DIS | SB_HIZ | M4)) \
48 MUX_VAL(CONTROL_PADCONF_CAM_D11, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
49 MUX_VAL(CONTROL_PADCONF_CAM_FLD, (IEN | DIS | SB_HIZ | M4)) \
50 MUX_VAL(CONTROL_PADCONF_CAM_HS, (IEN | PTD | EN | SB_LOW | SB_PD | M4)) \
51 MUX_VAL(CONTROL_PADCONF_CAM_PCLK, (IDIS | PTD | EN | SB_LOW | SB_PD | M4)) \
52 MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
[all …]
/rk3399_rockchip-uboot/board/technexion/tao3530/
H A Dtao3530.h149 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) \
164 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) \
193 MUX_VAL(CP(MMC2_DAT4), (IEN | PTU | EN | M4)) \
194 MUX_VAL(CP(MMC2_DAT5), (IEN | PTU | EN | M4)) \
195 MUX_VAL(CP(MMC2_DAT6), (IDIS | PTD | EN | M4)) \
196 MUX_VAL(CP(MMC2_DAT7), (IDIS | PTU | EN | M4)) \
201 MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M4)) \
203 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M4)) \
218 MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M4)) \
223 MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | EN | M4)) \
[all …]
H A Dtao3530.c36 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); in tao3530_revision()
43 MUX_VAL(CP(SYS_CLKREQ), (IEN | PTU | EN | M4)); in tao3530_revision()
/rk3399_rockchip-uboot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h41 {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */
42 {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */
43 {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */
44 {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */
/rk3399_rockchip-uboot/board/logicpd/am3517evm/
H A Dam3517evm.h126 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
163 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
178 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
192 MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
193 MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\
194 MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
195 MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
222 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
224 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
226 MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
[all …]
/rk3399_rockchip-uboot/board/ti/am3517crane/
H A Dam3517crane.h84 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
85 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
86 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
87 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
89 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
90 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
110 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M4))\
127 MUX_VAL(CP(GPMC_WAIT3), (IDIS | PTU | EN | M4))/*GPIO_65*/\
225 MUX_VAL(CP(MCSPI1_CLK), (IEN | PTU | EN | M4))/*GPIO_171 TP*/\
226 MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTU | EN | M4))/*GPIO_172 TP*/\
[all …]
/rk3399_rockchip-uboot/board/ti/evm/
H A Devm.h132 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
169 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
184 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
231 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\
233 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\
235 MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\
237 MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\
277 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\
279 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\
298 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\
[all …]
/rk3399_rockchip-uboot/board/logicpd/omap3som/
H A Domap3logic.c192 MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M4)); in board_late_init()
368 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)); /*GPIO_64*/ in set_muxconf_regs()
375 MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)); /*GPIO_98*/ in set_muxconf_regs()
389 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)); /*GPIO_167*/ in set_muxconf_regs()
439 MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/ in set_muxconf_regs()
440 MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)); /*GPIO_153*/ in set_muxconf_regs()
486 MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)); /*GPIO_175*/ in set_muxconf_regs()
487 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)); /*GPIO_176*/ in set_muxconf_regs()
499 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)); /*GPIO_2*/ in set_muxconf_regs()
500 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)); /*GPIO_3 */ in set_muxconf_regs()
[all …]

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