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Searched refs:LPDDR2 (Results 1 – 14 of 14) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h14 LPDDR2 = 5, enumerator
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A DKconfig32 3 for DDR3, 5 for LPDDR2, 6 for LPDDR3, 7 for LPDDR4, all other
H A Dsdram-px30-lpddr2-detect-333.inc28 .dramtype = LPDDR2,
H A Dsdram_px30.c217 sdram_params->base.dramtype == LPDDR2) && in set_ctl_address_map()
461 } else if (sdram_params->base.dramtype == LPDDR2) { in sdram_init_()
512 if (dram_type == LPDDR2) in dram_detect_cap()
H A Ddmc_fsp.c393 else if (dram_type == LPDDR2) in dmc_fsp_probe()
H A Dsdram_phy_px30.c65 if (dram_type == LPDDR2) in sdram_phy_set_ds_odt()
H A Dsdram_rk322x.c446 if (dramtype == LPDDR2) { in pctl_cfg()
488 case LPDDR2: in phy_cfg()
502 if (sdram_params->base.dramtype == LPDDR2) in phy_cfg()
H A Dsdram_common.c35 case LPDDR2: in sdram_print_dram_type()
357 } else if (dram_type == LPDDR3 || dram_type == LPDDR2) { in sdram_detect_dbw()
H A Dsdram_rk3308.c527 if (params_priv->ddr_config_t.ddr_type == LPDDR2) { in set_ds_odt()
728 case LPDDR2: in modify_sdram_params()
H A Dsdram_rv1108_pctl_phy.c387 case LPDDR2: in phy_cfg()
H A Dsdram_rv1126.c2734 if (dram_type == LPDDR2) in dram_detect_cap()
/rk3399_rockchip-uboot/board/freescale/mx6qarm2/
H A Dimximage_mx6dl.cfg149 /*LPDDR2 ZQ params */
193 * a. DQS gating is not relevant for LPDDR2. DSQ gating calibration section
/rk3399_rockchip-uboot/board/ccv/xpress/
H A Dimximage.cfg146 * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
/rk3399_rockchip-uboot/drivers/power/
H A DKconfig205 On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V.
209 LPDDR2, and the codec. It should be 1.8V.