| /rk3399_rockchip-uboot/board/freescale/bsc9131rdb/ |
| H A D | README | 46 . 32-Kbyte L1 instruction cache
47 . 32-Kbyte L1 data cache
54 . 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
55 . 32 Kbyte 8-way level 1 data cache (L1 DCache)
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| /rk3399_rockchip-uboot/arch/mips/ |
| H A D | Kconfig | 342 The total size of the L1 Dcache, if known at compile time.
348 The size of L1 Dcache lines, if known at compile time.
354 The total size of the L1 ICache, if known at compile time.
360 The size of L1 Icache lines, if known at compile time.
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| /rk3399_rockchip-uboot/board/freescale/ls1021aqds/ |
| H A D | README | 23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
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| /rk3399_rockchip-uboot/board/freescale/ls1021atwr/ |
| H A D | README | 23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
30 - 32 Kbyte L1 Instruction Cache and Data Cache for each core (ECC protection)
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| /rk3399_rockchip-uboot/board/freescale/bsc9132qds/ |
| H A D | README | 46 - 32 KB, 8-way, level 1 instruction cache (L1 ICache)
47 - 32 KB, 8-way, level 1 data cache (L1 DCache)
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/ |
| H A D | start.S | 248 @ lines allocate in the L1 or L2 cache.
250 @ lines allocate in the L1 cache.
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| H A D | README.soc | 95 A53 processor, with 32 KB of parity protected L1-I cache,
96 32 KB of ECC protected L1-D cache, as well as 256 KB of
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| /rk3399_rockchip-uboot/arch/arm/dts/ |
| H A D | rk3528.dtsi | 191 opp-microvolt-L1 = <862500 862500 1100000>;
202 opp-microvolt-L1 = <925000 925000 1100000>;
213 opp-microvolt-L1 = <1000000 1000000 1100000>;
224 opp-microvolt-L1 = <1050000 1050000 1100000>;
235 opp-microvolt-L1 = <1087500 1087500 1100000>;
865 opp-microvolt-L1 = <837500 837500 1000000>;
871 opp-microvolt-L1 = <887500 887500 1000000>;
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| H A D | rk3506.dtsi | 234 opp-microvolt-L1 = <887500 887500 1000000>;
247 opp-microvolt-L1 = <925000 925000 1000000>;
260 opp-microvolt-L1 = <962500 962500 1000000>;
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| /rk3399_rockchip-uboot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PB | 48 0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
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| H A D | README.P1010RDB-PA | 66 0xffd0_0000 0xffd0_3fff L1 for Stack 16K Cacheable TLB0
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.b4860qds | 45 . 32 Kbyte L1 ICache per e6500/SC3900 core
46 . 32 Kbyte L1 DCache per e6500/SC3900 core
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| H A D | README.POST | 415 This test will verify the CPU cache (L1 cache). The test will
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| /rk3399_rockchip-uboot/common/spl/ |
| H A D | spl_fit_tb_arm64.S | 70 .L1: label
137 b .L1
161 b .L1
167 b .L1
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| H A D | spl_fit_tb_px30.S | 70 .L1: label
137 b .L1
161 b .L1
167 b .L1
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| H A D | spl_fit_tb_rv1106.S | 72 .L1: label
130 b .L1
154 b .L1
160 b .L1
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| H A D | spl_fit_tb_rv1126b.S | 70 .L1: label
137 b .L1
161 b .L1
167 b .L1
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| H A D | spl_fit_tb_rv1126.S | 72 .L1: label
130 b .L1
154 b .L1
160 b .L1
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| /rk3399_rockchip-uboot/drivers/video/rk_eink/epdlut/ |
| H A D | pvi_waveform.S | 55 .L1: label
64 b .L1
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| /rk3399_rockchip-uboot/cmd/ddr_tool/ddr_test/ |
| H A D | ddr_test_rk1808.S | 132 .L1: label
270 b .L1
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| H A D | ddr_test_rk3328.S | 132 .L1: label
270 b .L1
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| H A D | ddr_test_px30.S | 132 .L1: label
270 b .L1
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