Searched refs:GPIO2_IOC_BASE (Results 1 – 5 of 5) sorted by relevance
39 #define GPIO2_IOC_BASE 0xff4d8000 macro43 #define GPIO3_IOC_BASE GPIO2_IOC_BASE74 writel(0xffff1111, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_0); in board_set_iomux()75 writel(0x00ff0011, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_1); in board_set_iomux()98 writel(0xffff0000, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_0); in board_unset_iomux()99 writel(0x00ff0000, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_1); in board_unset_iomux()
78 #define GPIO2_IOC_BASE 0xFF570000 macro102 #define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x40)106 #define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x40)169 #define UART4_RX_M0_ADDR (GPIO2_IOC_BASE + 0x40)173 #define UART4_TX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
123 #define GPIO2_IOC_BASE 0xFF548000 macro160 #define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x28)164 #define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x28)188 #define UART1_RX_M1_ADDR (GPIO2_IOC_BASE + 0x24)192 #define UART1_TX_M1_ADDR (GPIO2_IOC_BASE + 0x24)239 #define UART3_TX_M1_ADDR (GPIO2_IOC_BASE + 0x18)
43 #define GPIO2_IOC_BASE 0x20840000 macro214 writel(0x0F000000, GPIO2_IOC_BASE + GPIO2A_IOMUX_SEL_1_1); in arch_cpu_init()
144 #define GPIO2_IOC_BASE 0xFF060000 macro679 if (readl(GPIO2_IOC_BASE + GPIO2_IOC_IO_VSEL0) & POC_VCCIO2_VD_3V3) { in arch_cpu_init()