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Searched refs:GICD_CTLR (Results 1 – 5 of 5) sorted by relevance

/rk3399_rockchip-uboot/drivers/irq/
H A Dirq-gic.c67 val = gicd_readl(GICD_CTLR); in int_enable_distributor()
69 gicd_writel(val, GICD_CTLR); in int_enable_distributor()
76 val = gicd_readl(GICD_CTLR); in int_disable_distributor()
78 gicd_writel(val, GICD_CTLR); in int_disable_distributor()
253 gicd_save.ctlr = gicd_readl(GICD_CTLR); in gic_irq_suspend()
301 gicd_writel(0, GICD_CTLR); in gic_irq_resume()
343 gicd_writel(gicd_save.ctlr, GICD_CTLR); in gic_irq_resume()
375 gicd_writel(0, GICD_CTLR); in gic_irq_init()
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/
H A Dvirt-v7.c113 writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, in armv7_init_nonsec()
114 gic_dist_addr + GICD_CTLR); in armv7_init_nonsec()
/rk3399_rockchip-uboot/arch/arm/lib/
H A Dgic_64.S32 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
45 str w9, [x0, GICD_CTLR] /* Secure GICD_CTLR */
/rk3399_rockchip-uboot/arch/arm/include/asm/
H A Dgic.h11 #define GICD_CTLR 0x0000 macro
/rk3399_rockchip-uboot/drivers/cpu/
H A Drockchip_amp.c166 val = gicd_readl(GICD_CTLR); in setup_sync_bits_for_linux()
168 gicd_writel(val, GICD_CTLR); in setup_sync_bits_for_linux()