| /rk3399_rockchip-uboot/doc/device-tree-bindings/cpu/ |
| H A D | nios2.txt | 13 - reg: Contains CPU index.
14 - clock-frequency: Contains the clock frequency for CPU, in Hz.
19 - altr,reset-addr: Specifies CPU reset address
20 - altr,exception-addr: Specifies CPU exception address
23 - altr,has-initda: Specifies CPU support initda instruction, should be 1.
24 - altr,has-mmu: Specifies CPU support MMU support.
25 - altr,has-mul: Specifies CPU hardware multipy support.
26 - altr,has-div: Specifies CPU hardware divide support
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| /rk3399_rockchip-uboot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | psci.S | 85 @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped
86 @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for
89 @ Get the real CPU number
106 @ Affinity level 0 - CPU: only 0, 1 are valid in LS1021xa.
114 @ r1 = target CPU
120 @ Clear and Get the correct CPU number
135 @ Detect target CPU state
142 @ Reset target CPU
158 @ Do reset on target CPU
164 @ Wait target CPU up
[all …]
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| /rk3399_rockchip-uboot/ |
| H A D | config.mk | 26 CPU := $(CONFIG_SYS_CPU:"%"=%)
29 CPU := arm720t
44 CPUDIR=arch/$(ARCH)/cpu$(if $(CPU),/$(CPU),)
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| /rk3399_rockchip-uboot/arch/nds32/ |
| H A D | Makefile | 5 head-y := arch/nds32/cpu/$(CPU)/start.o
7 libs-y += arch/nds32/cpu/$(CPU)/
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| /rk3399_rockchip-uboot/arch/powerpc/ |
| H A D | Makefile | 5 head-y := arch/powerpc/cpu/$(CPU)/start.o
8 libs-y += arch/powerpc/cpu/$(CPU)/
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| /rk3399_rockchip-uboot/drivers/mailbox/ |
| H A D | Kconfig | 9 CPU to another CPU, or sometimes to dedicated HW modules. They form
10 the basis of a variety of inter-process/inter-CPU communication
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| /rk3399_rockchip-uboot/arch/arm/mach-exynos/ |
| H A D | Kconfig | 12 Samsung Exynos4 SoC family are based on ARM Cortex-A9 CPU. There
28 Samsung Exynos5 SoC family are based on ARM Cortex-A15 CPU (and
29 Cortex-A7 CPU in big.LITTLE configuration). There are multiple SoCs
37 Samsung Exynos7 SoC family are based on ARM Cortex-A57 CPU or
38 Cortex-A53 CPU (and some in a big.LITTLE configuration). There are
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| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/acpi/ |
| H A D | lpc.asl | 112 IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
113 IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
114 IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
116 IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
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| /rk3399_rockchip-uboot/doc/ |
| H A D | README.N1213 | 1 N1213 is a configurable hard/soft core of NDS32's N12 CPU family.
6 CPU Core
41 - Internal or external to CPU core.
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| H A D | README.NDS32 | 34 AndesCore CPU
36 Andes Technology has 4 families of CPU cores: N12, N10, N9, N8.
38 For details about N12 CPU family, please check doc/README.N1213.
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| H A D | I2C_Edge_Conditions | 5 and the CPU was reset. This may result in EEPROM data corruption.
11 4) The CPU is reset at this point.
13 Once the CPU reinitializes and the read is tried again:
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| H A D | README.ag101p | 4 AG101P is the mainline SoC produced by Andes Technology using N1213 CPU core
12 ADP-AG101P is the SoC with AG101 hardcore CPU.
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| H A D | README.mips | 38 * Probe CPU types, I-/D-cache and TLB size etc. automatically
52 * centralize/share more CPU code of MIPS32, MIPS64 and XBurst
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| /rk3399_rockchip-uboot/arch/m68k/ |
| H A D | Makefile | 5 head-y := arch/m68k/cpu/$(CPU)/start.o
7 libs-y += arch/m68k/cpu/$(CPU)/
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/ |
| H A D | psci.S | 31 @ converts CPU ID into FLOW_CTRL_CPUn_CSR offset
53 bl psci_get_cpu_id @ CPU ID => r0
73 bl psci_get_cpu_id @ CPU ID => r0
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| /rk3399_rockchip-uboot/drivers/cpu/ |
| H A D | Kconfig | 1 config CPU config
2 bool "Enable CPU drivers using Driver Model"
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| /rk3399_rockchip-uboot/arch/arc/ |
| H A D | Kconfig | 28 prompt "CPU selection"
37 Choose this option to build an U-Boot for ARC750D CPU.
44 Choose this option to build an U-Boot for ARC770D CPU.
109 Build kernel for Big Endian Mode of ARC CPU
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| H A D | Makefile | 5 libs-y += arch/arc/cpu/$(CPU)/
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| /rk3399_rockchip-uboot/arch/x86/include/asm/arch-baytrail/acpi/ |
| H A D | lpc.asl | 186 IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */
187 IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */
188 IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */
190 IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */
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| /rk3399_rockchip-uboot/drivers/sysreset/ |
| H A D | Kconfig | 11 Enable system reset drivers which can be used to reset the CPU or
20 Enable system reset drivers which can be used to reset the CPU or
29 Enable system reset drivers which can be used to reset the CPU or
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| /rk3399_rockchip-uboot/arch/sh/ |
| H A D | Makefile | 7 libs-y += arch/sh/cpu/$(CPU)/
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| H A D | config.mk | 13 ifeq ($(CPU),sh2)
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| /rk3399_rockchip-uboot/arch/powerpc/cpu/mpc8xx/ |
| H A D | Kconfig | 1 menu "mpc8xx CPU"
17 prompt "CPU select"
29 int "CPU GCLK Frequency"
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| /rk3399_rockchip-uboot/doc/device-tree-bindings/firmware/ |
| H A D | nvidia,tegra186-bpmp.txt | 5 management, and reset control tasks from the CPU. The binding document
7 which can create the interprocessor communication (IPC) between the CPU
18 the IPC between CPU and BPMP is based on.
62 The shared memory area for the IPC TX and RX between CPU and BPMP are
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| /rk3399_rockchip-uboot/arch/arm/mach-tegra/tegra210/ |
| H A D | Kconfig | 18 P2371-0000 is a P2581 or P2530 CPU board married to a P2595 I/O
27 P2371-2180 (Jetson TX1 developer kit) is a P2180 CPU board married
|