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Searched refs:CKSEG1ADDR (Results 1 – 11 of 11) sorted by relevance

/rk3399_rockchip-uboot/board/imgtec/malta/
H A Dmalta.c39 void *reg = (void *)CKSEG1ADDR(MALTA_ASCIIPOS0); in malta_lcd_puts()
57 const void *reg = (const void *)CKSEG1ADDR(MALTA_REVISION); in malta_core_card()
129 reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); in _machine_restart()
141 io_base = CKSEG1ADDR(MALTA_GT_PCIIO_BASE); in board_early_init_f()
145 io_base = CKSEG1ADDR(MALTA_MSC01_PCIIO_BASE); in board_early_init_f()
175 gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE), in pci_init_board()
183 msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE), in pci_init_board()
186 CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE), in pci_init_board()
H A Dlowlevel_init.S32 PTR_LI t0, CKSEG1ADDR(MALTA_REVISION)
66 PTR_LI t1, CKSEG1ADDR(GT_DEF_BASE)
71 PTR_LI t1, CKSEG1ADDR(MALTA_GT_BASE)
98 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PBC_BASE)
120 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_BIU_BASE)
155 PTR_LI t0, CKSEG1ADDR(MALTA_MSC01_PCI_BASE)
/rk3399_rockchip-uboot/board/imgtec/boston/
H A Dboston-regs.h12 #define BOSTON_PLAT_BASE CKSEG1ADDR(0x17ffd000)
13 #define BOSTON_LCD_BASE CKSEG1ADDR(0x17fff000)
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S82 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
111 li t0, CKSEG1ADDR(AR933X_RTC_BASE)
136 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
158 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
234 li t0, CKSEG1ADDR(AR933X_SRIF_BASE)
272 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
H A Dddr.c282 addr_k1 = (void *)CKSEG1ADDR(0x2000); in ddr_tap_tuning()
/rk3399_rockchip-uboot/arch/mips/include/asm/
H A Daddrspace.h72 #define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) macro
79 #define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1) macro
139 #define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
H A Dcm.h46 return (void *)CKSEG1ADDR(CONFIG_MIPS_CM_BASE); in mips_cm_base()
H A Dio.h151 return (void __iomem *)(unsigned long)CKSEG1ADDR(phys_addr); in __ioremap_mode()
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dlowlevel_init.S102 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
115 li t0, CKSEG1ADDR(QCA953X_RTC_BASE)
128 li t0, CKSEG1ADDR(QCA953X_SRIF_BASE)
135 li t0, CKSEG1ADDR(AR71XX_PLL_BASE)
179 li t0, CKSEG1ADDR(AR71XX_RESET_BASE)
/rk3399_rockchip-uboot/arch/mips/mach-pic32/include/mach/
H A Dpic32.h73 return (void __iomem *)CKSEG1ADDR(PIC32_CFG_BASE); in pic32_get_syscfg_base()
/rk3399_rockchip-uboot/arch/mips/lib/
H A Dcache_init.S152 PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
368 li t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)
410 PTR_LI t0, CKSEG1ADDR(CONFIG_MIPS_CM_BASE)