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Searched refs:u32 (Results 1 – 17 of 17) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_internal.c85 (((u32)pwrctrl->reg_spm_scp_mailbox_req & 0x1) << 8) | in __spm_set_power_control()
86 (((u32)pwrctrl->reg_spm_sspm_mailbox_req & 0x1) << 9) | in __spm_set_power_control()
87 (((u32)pwrctrl->reg_spm_sw_mailbox_req & 0x1) << 10) | in __spm_set_power_control()
88 ((((u32)pwrctrl->reg_spm_vcore_req | in __spm_set_power_control()
90 ((((u32)pwrctrl->reg_spm_vrf18_req | in __spm_set_power_control()
92 (((u32)pwrctrl->adsp_mailbox_state & 0x1) << 16) | in __spm_set_power_control()
93 (((u32)pwrctrl->apsrc_state & 0x1) << 17) | in __spm_set_power_control()
94 (((u32)pwrctrl->ddren_state & 0x1) << 18) | in __spm_set_power_control()
95 (((u32)pwrctrl->dvfs_state & 0x1) << 19) | in __spm_set_power_control()
96 (((u32)pwrctrl->emi_state & 0x1) << 20) | in __spm_set_power_control()
[all …]
H A Dmt_spm_suspend.c642 .val.u32 = 0, in mt_spm_suspend_enter()
688 event.val.u32 = 0; in mt_spm_suspend_resume()
693 event.val.u32 = MT_LPM_WAKE_MD_WAKEUP_DPMAIF; in mt_spm_suspend_resume()
695 event.val.u32 = MT_LPM_WAKE_MD_WAKEUP_CCIF0; in mt_spm_suspend_resume()
697 event.val.u32 = MT_LPM_WAKE_MD_WAKEUP_CCIF1; in mt_spm_suspend_resume()
H A Dmt_spm_idle.c548 .val.u32 = 0, in mt_spm_idle_generic_enter()
579 .val.u32 = 0, in mt_spm_idle_generic_resume()
H A Dmt_spm_internal.h1075 typedef uint32_t u32; typedef
/rk3399_ARM-atf/docs/components/
H A Dffa-manifest-binding.rst24 - value type: <u32>
35 - An array of comma separated tuples each consisting of 4 <u32> values,
38 - These 4 <u32> values are packed similar to the UUID register mapping
44 - value type: <u32>
48 - value type: <u32>
56 - value type: <u32>
67 - value type: <u32>
75 - value type: <u32>
94 - value type: <u32>
102 - value type: <u32>
[all …]
H A Dcot-binding.rst52 Value type: <u32>
197 Value type: <u32>
265 Value type: <u32>
275 Value type: <u32>
287 Value type: <u32>
295 Value type: <u32>
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_suspend.c447 .val.u32 = 0, in mt_spm_suspend_enter()
492 event.val.u32 = 0; in mt_spm_suspend_resume()
497 event.val.u32 = MT_LPM_WAKE_MD_WAKEUP_DPMAIF; in mt_spm_suspend_resume()
499 event.val.u32 = MT_LPM_WAKE_MD_WAKEUP_CCIF0; in mt_spm_suspend_resume()
501 event.val.u32 = MT_LPM_WAKE_MD_WAKEUP_CCIF1; in mt_spm_suspend_resume()
H A Dmt_spm_idle.c374 .val.u32 = 0, in mt_spm_idle_generic_enter()
402 .val.u32 = 0, in mt_spm_idle_generic_resume()
/rk3399_ARM-atf/plat/imx/common/sci/
H A Dipc.c90 &(msg->DATA.u32[count - 1])); in sc_ipc_read()
116 msg->DATA.u32[count - 1]); in sc_ipc_write()
/rk3399_ARM-atf/plat/imx/common/include/sci/
H A Dsci_rpc.h35 #define RPC_U32(MSG, IDX) ((MSG)->DATA.u32[(IDX) / 4U])
72 uint32_t u32[(SC_RPC_MAX_MSG - 1U)]; member
/rk3399_ARM-atf/docs/components/measured_boot/
H A Devent_log.rst34 - value type: <u32>
38 - value type: <u32>
/rk3399_ARM-atf/docs/components/fconf/
H A Dfconf_properties.rst28 - value type: <u32>
32 - value type: <u32>
H A Dtb_fw_bindings.rst125 - value type: <u32>
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_idle.c345 .val.u32 = 0U, in mt_spm_idle_generic_enter()
359 .val.u32 = 0U, in mt_spm_idle_generic_resume()
H A Dmt_spm_suspend.c396 .val.u32 = 0U, in mt_spm_suspend_enter()
408 .val.u32 = 0U, in mt_spm_suspend_resume()
/rk3399_ARM-atf/plat/mediatek/include/lpm/
H A Dmt_lp_api.h29 unsigned int u32; member
/rk3399_ARM-atf/plat/mediatek/include/lpm_v2/
H A Dmt_lp_api.h29 unsigned int u32; member