xref: /rk3399_ARM-atf/plat/mediatek/include/lpm_v2/mt_lp_api.h (revision cf2df874cd09305ac7282fadb0fef6be597dfffb)
1*da8cc41bSWenzhen Yu /*
2*da8cc41bSWenzhen Yu  * Copyright (c) 2025, MediaTek Inc. All rights reserved.
3*da8cc41bSWenzhen Yu  *
4*da8cc41bSWenzhen Yu  * SPDX-License-Identifier: BSD-3-Clause
5*da8cc41bSWenzhen Yu  */
6*da8cc41bSWenzhen Yu 
7*da8cc41bSWenzhen Yu #ifndef MT_LP_API_H
8*da8cc41bSWenzhen Yu #define MT_LP_API_H
9*da8cc41bSWenzhen Yu 
10*da8cc41bSWenzhen Yu #include <lpm_v2/mt_lp_rm.h>
11*da8cc41bSWenzhen Yu 
12*da8cc41bSWenzhen Yu #if MTK_PUBEVENT_ENABLE
13*da8cc41bSWenzhen Yu #include <vendor_pubsub_events.h>
14*da8cc41bSWenzhen Yu #endif
15*da8cc41bSWenzhen Yu 
16*da8cc41bSWenzhen Yu /* UFS clk enum for PLAT_RC_CLKBUF_STATUS */
17*da8cc41bSWenzhen Yu enum rc_update_ex_ufs_ref_clk {
18*da8cc41bSWenzhen Yu 	UFS_REF_CLK_OFF = 0,
19*da8cc41bSWenzhen Yu 	UFS_REF_CLK_ON,
20*da8cc41bSWenzhen Yu };
21*da8cc41bSWenzhen Yu 
22*da8cc41bSWenzhen Yu /* Enum for flight mode  */
23*da8cc41bSWenzhen Yu enum rc_update_ex_flight_mode {
24*da8cc41bSWenzhen Yu 	FLIGHT_MODE_OFF = 0,
25*da8cc41bSWenzhen Yu 	FLIGHT_MODE_ON,
26*da8cc41bSWenzhen Yu };
27*da8cc41bSWenzhen Yu 
28*da8cc41bSWenzhen Yu struct mt_lpm_pubevent_data {
29*da8cc41bSWenzhen Yu 	unsigned int u32;
30*da8cc41bSWenzhen Yu };
31*da8cc41bSWenzhen Yu 
32*da8cc41bSWenzhen Yu enum mt_lpm_pubevents_id {
33*da8cc41bSWenzhen Yu 	MT_LPM_PUBEVENTS_BBLPM_ENTER,
34*da8cc41bSWenzhen Yu 	MT_LPM_PUBEVENTS_BBLPM_LEAVE,
35*da8cc41bSWenzhen Yu 	MT_LPM_PUBEVENTS_TARGET_CORE,
36*da8cc41bSWenzhen Yu 	MT_LPM_PUBEVENTS_SYS_POWER_OFF,
37*da8cc41bSWenzhen Yu 	MT_LPM_PUBEVENTS_SYS_POWER_ON,
38*da8cc41bSWenzhen Yu };
39*da8cc41bSWenzhen Yu 
40*da8cc41bSWenzhen Yu struct mt_lp_publish_event {
41*da8cc41bSWenzhen Yu 	unsigned int id;
42*da8cc41bSWenzhen Yu 	struct mt_lpm_pubevent_data val;
43*da8cc41bSWenzhen Yu 	unsigned int level;
44*da8cc41bSWenzhen Yu };
45*da8cc41bSWenzhen Yu 
46*da8cc41bSWenzhen Yu #if MTK_PUBEVENT_ENABLE
47*da8cc41bSWenzhen Yu #define MT_LP_PUBLISH_EVENT(x) ({ \
48*da8cc41bSWenzhen Yu 	PUBLISH_EVENT_ARG(lpm_publish_event, (const void *)(x)); })
49*da8cc41bSWenzhen Yu #define MT_LP_SUSPEND_PUBLISH_EVENT(x) ({ \
50*da8cc41bSWenzhen Yu 	PUBLISH_EVENT_ARG(suspend_publish_event, (const void *)(x)); })
51*da8cc41bSWenzhen Yu 
52*da8cc41bSWenzhen Yu #define MT_LP_SUBSCRIBE_SUSPEND(func) \
53*da8cc41bSWenzhen Yu 	SUBSCRIBE_TO_EVENT(suspend_publish_event, func)
54*da8cc41bSWenzhen Yu #define MT_LP_SUBSCRIBE_LPM(func) \
55*da8cc41bSWenzhen Yu 	SUBSCRIBE_TO_EVENT(lpm_publish_event, func)
56*da8cc41bSWenzhen Yu #else
57*da8cc41bSWenzhen Yu #define MT_LP_PUBLISH_EVENT(x)	({ (void)x; })
58*da8cc41bSWenzhen Yu #define MT_LP_SUSPEND_PUBLISH_EVENT(x)	({ (void)x; })
59*da8cc41bSWenzhen Yu #define MT_LP_SUBSCRIBE_SUSPEND(func)
60*da8cc41bSWenzhen Yu #define MT_LP_SUBSCRIBE_LPM(func)
61*da8cc41bSWenzhen Yu #endif
62*da8cc41bSWenzhen Yu 
63*da8cc41bSWenzhen Yu /* MTK low power API types for audio */
64*da8cc41bSWenzhen Yu enum mt_lp_api_audio_type {
65*da8cc41bSWenzhen Yu 	AUDIO_AFE_ENTER,
66*da8cc41bSWenzhen Yu 	AUDIO_AFE_LEAVE,
67*da8cc41bSWenzhen Yu 	AUDIO_DSP_ENTER,
68*da8cc41bSWenzhen Yu 	AUDIO_DSP_LEAVE,
69*da8cc41bSWenzhen Yu };
70*da8cc41bSWenzhen Yu 
71*da8cc41bSWenzhen Yu /* MTK low power API types for usb */
72*da8cc41bSWenzhen Yu enum mt_lp_api_usb_type {
73*da8cc41bSWenzhen Yu 	LPM_USB_ENTER,
74*da8cc41bSWenzhen Yu 	LPM_USB_LEAVE,
75*da8cc41bSWenzhen Yu 	USB_HEADSET_ENTER,
76*da8cc41bSWenzhen Yu 	USB_HEADSET_LEAVE,
77*da8cc41bSWenzhen Yu };
78*da8cc41bSWenzhen Yu 
79*da8cc41bSWenzhen Yu int mt_audio_update(int type);
80*da8cc41bSWenzhen Yu int mt_usb_update(int type);
81*da8cc41bSWenzhen Yu 
82*da8cc41bSWenzhen Yu /* MTK Low Power Scenario Types for logging */
83*da8cc41bSWenzhen Yu enum mtk_lp_scenario_status {
84*da8cc41bSWenzhen Yu 	AUDIO_AFE,
85*da8cc41bSWenzhen Yu 	AUDIO_DSP,
86*da8cc41bSWenzhen Yu 	USB_HEADSET,
87*da8cc41bSWenzhen Yu 	MTK_LP_SCENE_NUM,
88*da8cc41bSWenzhen Yu };
89*da8cc41bSWenzhen Yu 
90*da8cc41bSWenzhen Yu /* MTK Low Power API Types for CCCI */
91*da8cc41bSWenzhen Yu enum mt_lp_api_ccci_type {
92*da8cc41bSWenzhen Yu 	CCCI_AP_MDSRC_REQUEST,
93*da8cc41bSWenzhen Yu 	CCCI_AP_MDSRC_RELEASE,
94*da8cc41bSWenzhen Yu 	CCCI_AP_MDSRC_ACK,
95*da8cc41bSWenzhen Yu 	CCCI_AP_MDSRC_GET_SETTLE,
96*da8cc41bSWenzhen Yu 	CCCI_AP_IS_MD_SLEEP,
97*da8cc41bSWenzhen Yu };
98*da8cc41bSWenzhen Yu 
99*da8cc41bSWenzhen Yu /* System power level */
100*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_APMCU	BIT(0)
101*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_DRAM	BIT(1)
102*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_SYSPLL	BIT(2)
103*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_PMIC_LP	BIT(3)
104*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_BUS26M	BIT(4)
105*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_VCORE0V	BIT(5)
106*da8cc41bSWenzhen Yu #define MT_LP_SYSPOWER_LEVEL_SUSPEND	BIT(6)
107*da8cc41bSWenzhen Yu 
108*da8cc41bSWenzhen Yu 
109*da8cc41bSWenzhen Yu enum mt_lpm_pubevent_wake_src {
110*da8cc41bSWenzhen Yu 	MT_LPM_WAKE_MD_WAKEUP_CCIF0 = 1,
111*da8cc41bSWenzhen Yu 	MT_LPM_WAKE_MD_WAKEUP_CCIF1,
112*da8cc41bSWenzhen Yu 	MT_LPM_WAKE_MD_WAKEUP_CLDMA,
113*da8cc41bSWenzhen Yu 	MT_LPM_WAKE_MD_WAKEUP_DPMAIF,
114*da8cc41bSWenzhen Yu 	MT_LPM_WAKE_MD_WDT,
115*da8cc41bSWenzhen Yu };
116*da8cc41bSWenzhen Yu 
117*da8cc41bSWenzhen Yu /* MTK Low Power API Types for GPUEB */
118*da8cc41bSWenzhen Yu enum mt_lp_api_gpueb_type {
119*da8cc41bSWenzhen Yu 	GPUEB_PLL_EN,
120*da8cc41bSWenzhen Yu 	GPUEB_PLL_DIS,
121*da8cc41bSWenzhen Yu 	GPUEB_GET_PWR_STATUS,
122*da8cc41bSWenzhen Yu 	GPUEB_GET_MFG0_PWR_CON,
123*da8cc41bSWenzhen Yu };
124*da8cc41bSWenzhen Yu 
125*da8cc41bSWenzhen Yu int mt_ccci_hwctrl(int type, void *priv);
126*da8cc41bSWenzhen Yu int mt_gpueb_hwctrl(int type, void *priv);
127*da8cc41bSWenzhen Yu uint64_t mt_get_lp_scenario_status(void);
128*da8cc41bSWenzhen Yu 
129*da8cc41bSWenzhen Yu #endif /* MT_LP_API_H */
130