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Searched refs:ref_clk (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/stratix10/soc/
H A Ds10_clock_manager.c203 uint32_t data32, mdiv, refclkdiv, ref_clk; in get_ref_clk() local
209 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
212 ref_clk = ALT_CLKMGR_INTOSC_HZ; in get_ref_clk()
216 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
219 ref_clk = 0; in get_ref_clk()
228 ref_clk = (ref_clk / refclkdiv) * (6 + mdiv); in get_ref_clk()
230 return ref_clk; in get_ref_clk()
236 uint32_t clk_psrc, ref_clk; in get_clk_freq() local
254 ref_clk = get_ref_clk(mmio_read_32(pllglob_reg)); in get_clk_freq()
259 ref_clk = (ref_clk / pllc_div) / (clk_psrc + 1); in get_clk_freq()
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/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_clock_manager.c281 uint32_t arefclkdiv, ref_clk; in get_ref_clk() local
287 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
290 ref_clk = CLKMGR_INTOSC_HZ; in get_ref_clk()
294 ref_clk = mmio_read_32(scr_reg); in get_ref_clk()
297 ref_clk = 0; in get_ref_clk()
303 ref_clk /= arefclkdiv; in get_ref_clk()
305 return ref_clk; in get_ref_clk()
311 uint32_t clk_psrc, mdiv, ref_clk; in get_clk_freq() local
331 ref_clk = get_ref_clk(mmio_read_32(pllglob_reg)); in get_clk_freq()
333 ref_clk *= mdiv; in get_clk_freq()
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/rk3399_ARM-atf/drivers/marvell/comphy/
H A Dphy-comphy-3700.c291 uint32_t offset, data = 0, ref_clk; in mvebu_a3700_comphy_sata_power_on() local
325 ref_clk = REF_FREF_SEL_SERDES_40MHZ; in mvebu_a3700_comphy_sata_power_on()
327 ref_clk = REF_FREF_SEL_SERDES_25MHZ; in mvebu_a3700_comphy_sata_power_on()
329 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA, in mvebu_a3700_comphy_sata_power_on()
616 uint32_t mask, data, cfg, ref_clk; in mvebu_a3700_comphy_usb3_power_on() local
705 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; in mvebu_a3700_comphy_usb3_power_on()
710 ref_clk = REF_FREF_SEL_PCIE_USB3_25MHZ; in mvebu_a3700_comphy_usb3_power_on()
718 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk; in mvebu_a3700_comphy_usb3_power_on()
812 uint32_t ref_clk; in mvebu_a3700_comphy_pcie_power_on() local
862 ref_clk = REF_FREF_SEL_PCIE_USB3_40MHZ; in mvebu_a3700_comphy_pcie_power_on()
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/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c364 uint32_t arefclkdiv, ref_clk, mdiv; in get_ref_clk() local
373 ref_clk = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)); in get_ref_clk()
377 ref_clk = CLKMGR_INTOSC_HZ; in get_ref_clk()
381 ref_clk = mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2)); in get_ref_clk()
385 ref_clk = 0; in get_ref_clk()
392 ref_clk /= arefclkdiv; in get_ref_clk()
396 ref_clk *= mdiv; in get_ref_clk()
398 VERBOSE("CLKMGR: %s: ref_clk %u\n", __func__, ref_clk); in get_ref_clk()
399 return ref_clk; in get_ref_clk()
/rk3399_ARM-atf/plat/intel/soc/stratix10/include/
H A Ds10_clock_manager.h97 uint32_t get_l3_clk(uint32_t ref_clk);