| #
9c653440 |
| 10-Jan-2024 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes Id85b2541,I4d253e2f into integration
* changes:
fix(intel): update system counter back to 400MHz
fix(intel): revert back to use L4 clock
|
| #
d0e400b3 |
| 22-Dec-2023 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): revert back to use L4 clock
Using mpu_peri as the clock source will caused the system
timer vary. System timer shall get from a static clock
source.
L4 and L3 clock are both the same at
fix(intel): revert back to use L4 clock
Using mpu_peri as the clock source will caused the system
timer vary. System timer shall get from a static clock
source.
L4 and L3 clock are both the same at the moment.
There shall be a hardware update to differentiate the clock pll.
To keep this as dormant function for now.
Change-Id: I4d253e2f24a74cbec59bfcbf0e8547abbe3643a8
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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| #
9118bdf4 |
| 19-Dec-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): fix hardcoded mpu frequency ticks" into integration
|
| #
150d2be0 |
| 07-Jul-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06a
fix(intel): fix hardcoded mpu frequency ticks
This patch is used to update the hardcoded mpu freq ticks
to obtain the freqq from the hardware setting itself.
Change-Id: I7b9eb49f2512b85fb477110f06ae86ef289aee58
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
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|
| #
816c27fb |
| 23-May-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes I38545567,I2f52d3ea into integration
* changes:
feat(intel): restructure sys mgr for S10/N5X
feat(intel): restructure sys mgr for Agilex
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| #
b653f3ca |
| 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): restructure sys mgr for S10/N5X
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for
feat(intel): restructure sys mgr for S10/N5X
This patch is to restructure system manager. Move platform dependent
MACROs to individual platform system manager. Common system manager will
remain for those common declaration only.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I385455671413e154d04a879d33fdd774fcfefbd6
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|
| #
ffc56bd0 |
| 17-Apr-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes I43a9d83c,Ibfaa47fb into integration
* changes:
fix(intel): fix Agilex and N5X clock manager to main PLL C0
feat(intel): implement timer init divider via CPU frequency for N5X
|
| #
02a9d70c |
| 23-Jun-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): implement timer init divider via CPU frequency for N5X
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signe
feat(intel): implement timer init divider via CPU frequency for N5X
Get CPU frequency and update the timer init div with it.
The timer is vary based on the CPU frequency instead of hardcoded.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibfaa47fb7a25176eebf06f4828bf9729d56f12ed
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| #
13ce03aa |
| 06-May-2022 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC" into integration
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| #
026dfed8 |
| 06-May-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(intel): implement timer init divider via cpu frequency. (#1)" into integration
|
| #
f65bdf3a |
| 06-Apr-2022 |
BenjaminLimJL <jit.loon.lim@intel.com> |
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The impl
feat(intel): implement timer init divider via cpu frequency. (#1)
Get cpu frequency and update the timer init div with it.
The timer is vary based on the cpu frequency instead of hardcoded.
The implementation shall apply to only Agilex and S10
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I61684d9762ad34e5a60b8b176b60c8848db4b422
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|
| #
bb0fcc7e |
| 05-May-2022 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC
SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.
Signed-off-by: Lo
feat(intel): add SMPLSEL and DRVSEL setup for Stratix 10 MMC
SMPLSEL and DRVSEL values need to updated in
DWMMC for the IP to work correctly. This apply
on Stratix 10 device only.
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: Ibd799a65890690682e27e4cbbc85e83ea03d51fc
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|
| #
b33772eb |
| 04-Dec-2019 |
Mark Dykes <mardyk01@review.trustedfirmware.org> |
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform c
Merge changes from topic "platform-refactor" into integration
* changes:
intel: Refactor common platform code [4/5]
intel: Refactor common platform code [3/5]
intel: Refactor common platform code [2/5]
intel: Refactor common platform code [1/5]
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|
| #
328718f2 |
| 23-Oct-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both
intel: Refactor common platform code [1/5]
Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.
Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
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|
| #
5dbdf8e4 |
| 05-Sep-2019 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "intel: stratix10: Fix reliance on hard coded clock information" into integration
|
| #
fea24b88 |
| 30-Jul-2019 |
Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.ha
intel: stratix10: Fix reliance on hard coded clock information
Extract clock information for UART, MMC & Watchdog from the platform
rather than hard code it
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I2582bd34a6da97bd75d5ccba5f93840e65f26b03
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|
| #
d037bec9 |
| 01-Apr-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1898 from hadi-asyrafi/watchdog
intel: Enable watchdog timer on Intel S10 platform
|
| #
10e70f87 |
| 19-Mar-2019 |
Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com> |
intel: Enable watchdog timer on Intel S10 platform
Watchdog driver support & enablement during platform setup
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@inte
intel: Enable watchdog timer on Intel S10 platform
Watchdog driver support & enablement during platform setup
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
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|
| #
6ce30346 |
| 04-Feb-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1783 from thloh85-intel/integration_v2
plat: intel: Add BL2 support for Stratix 10 SoC
|
| #
9d82ef26 |
| 04-Feb-2019 |
Loh Tien Hock <tien.hock.loh@intel.com> |
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scru
plat: intel: Add BL2 support for Stratix 10 SoC
This adds BL2 support for Intel Stratix 10 SoC FPGA.
Functionality includes:
- Release and setup peripherals from reset
- Calibrate DDR
- ECC DDR Scrubbing
- Load FIP (bl31 and bl33)
Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>
show more ...
|