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/rk3399_ARM-atf/fdts/
H A Dmorello-coresight.dtsi30 port {
53 port {
76 port {
99 port {
110 port {
119 port@0 {
125 port@1 {
137 port {
146 port@0 {
152 port@1 {
[all …]
H A Dn1sdp-single-chip.dts54 port {
73 port {
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c151 uint32_t port = GET_GPIO_PORT(gpio_number); in gpio_get_clock() local
152 assert(port < 5U); in gpio_get_clock()
154 const struct port_info *info = &port_info[port]; in gpio_get_clock()
172 uint32_t port = GET_GPIO_PORT(gpio_number); in gpio_put_clock() local
173 const struct port_info *info = &port_info[port]; in gpio_put_clock()
180 uint32_t port = GET_GPIO_PORT(gpio); in get_pull() local
185 assert(port < 5U); in get_pull()
186 const struct port_info *info = &port_info[port]; in get_pull()
199 uint32_t port = GET_GPIO_PORT(gpio); in set_pull() local
204 assert(port < 5U); in set_pull()
[all …]
/rk3399_ARM-atf/include/dt-bindings/pinctrl/
H A Dstm32-pinfunc.h32 #define PIN_NO(port, line) (((port) - 'A') * 0x10 + (line)) argument
34 #define STM32_PINMUX(port, line, mode) (((PIN_NO(port, line)) << 8) | (mode)) argument
/rk3399_ARM-atf/plat/mediatek/drivers/iommu/
H A Dmtk_iommu_smc.c12 #define SMI_LARB_NON_SEC_CON(port) (0x380 + ((port) << 2)) argument
14 #define SMI_LARB_SEC_CON_INT(port) (0xf00 + ((port) << 2)) argument
15 #define SMI_LARB_SEC_CON(port) (0xf80 + ((port) << 2)) argument
21 #define SMI_MMU_EN(port) (0x1 << (port)) argument
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_security.c51 static volatile struct rgn_map_reg *get_rgn_map_reg(uint32_t base, int region, int port) in get_rgn_map_reg() argument
53 uint64_t addr = base + 0x100 + 0x10 * region + 0x400 * (uint64_t)port; in get_rgn_map_reg()
58 int port) in get_rgn_attr_reg() argument
60 uint64_t addr = base + 0x104 + 0x10 * region + 0x400 * (uint64_t)port; in get_rgn_attr_reg()
H A Dhikey_ddr.c1357 unsigned int port, data; in init_ddrc_qos() local
1361 port = 0; in init_ddrc_qos()
1362 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); in init_ddrc_qos()
1363 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x11111111); in init_ddrc_qos()
1364 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x11111111); in init_ddrc_qos()
1367 for (port = 3; port <= 4; port++) { in init_ddrc_qos()
1368 mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); in init_ddrc_qos()
1369 mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x77777777); in init_ddrc_qos()
1370 mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x77777777); in init_ddrc_qos()
1373 port = 1; in init_ddrc_qos()
[all …]
/rk3399_ARM-atf/plat/allwinner/common/
H A Dsunxi_common.c86 void sunxi_set_gpio_out(char port, int pin, bool level_high) in sunxi_set_gpio_out() argument
90 if (port < 'A' || port > 'L') in sunxi_set_gpio_out()
92 if (port == 'L') in sunxi_set_gpio_out()
95 port_base = SUNXI_PIO_BASE + (port - 'A') * 0x24; in sunxi_set_gpio_out()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dbl31_setup.c185 #define SATA_APBT_IDM_PORT_REG(port, reg) \ argument
186 (((port/4) << 12) + reg)
188 #define SATA_IDM_PORT_REG(port, reg) ((port << 12) + reg) argument
190 #define SATA_PORT_REG(port, reg) \ argument
191 (((port%4) << 16) + ((port/4) << 20) + reg)
201 static uint32_t brcm_stingray_get_sata_port(unsigned int port) in brcm_stingray_get_sata_port() argument
203 return sr_b0_sata_port[port]; in brcm_stingray_get_sata_port()
208 unsigned int port = 0; in brcm_stingray_sata_init() local
217 for (port = 0; port < USE_SATA_PORTS; port++) { in brcm_stingray_sata_init()
219 sata_port = brcm_stingray_get_sata_port(port); in brcm_stingray_sata_init()
/rk3399_ARM-atf/docs/plat/
H A Dmeson-axg.rst7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
23 This port has been tested on a A113D board. After building it, follow the
25 by the one built from this port.
H A Dmeson-gxbb.rst7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested in a ODROID-C2. After building it, follow the
24 by the one built from this port.
H A Dmeson-g12a.rst7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
22 This port has been tested on a SEI510 board. After building it, follow the
24 mentioned **bl31.img** by the one built from this port.
H A Dmeson-gxl.rst7 This port is a minimal implementation of BL31 capable of booting mainline U-Boot
28 This port has been tested on a Lepotato. After building it, follow the
30 mentioned **bl31.img** by the one built from this port.
H A Drpi5.rst7 This port is a minimal BL31 implementation capable of booting 64-bit EL2
10 **IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
65 By default, all boot stages print messages to the dedicated UART debug port.
71 This port is largely based on the RPi 4 one.
76 port.
H A Drpi4.rst8 This port is a minimal port to support loading non-secure EL2 payloads such
12 **IMPORTANT NOTE**: This port isn't secure. All of the memory used is DRAM,
51 TF-A port design
54 In contrast to the existing Raspberry Pi 3 port this one here is a BL31-only
55 port, also it deviates quite a lot from the RPi3 port in many other ways.
H A Drcar-gen3.rst37 The current TF-A port has been tested on the R-Car H3 Salvator-X
69 On the rcar-gen3 the BOOTROM starts the cpu at EL3; for this port BL2
104 the H3 SiP Salvator-X development system used in this port.
127 Until it gets merged into OP-TEE, the port requires Renesas'
138 The port has beent tested using mainline uboot.
145 The port has beent tested using mainline kernel.
H A Drz-g2.rst41 The current TF-A port has been tested on the HiHope RZ/G2M
69 On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2
95 the HiHope RZ/G2M development kit used in this port.
116 The port has beent tested using mainline uboot with HiHope RZ/G2M board
124 The port has beent tested using mainline kernel.
/rk3399_ARM-atf/docs/plat/marvell/armada/misc/
H A Dmvebu-io-win.rst13 - **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
17 - **0x5** = PCIe port
43 {0x00000000fe000000, 0x000000001f00000, PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
/rk3399_ARM-atf/
H A D.gitreview3 port=29418
/rk3399_ARM-atf/docs/plat/marvell/armada/
H A Duart-booting.rst37 > stty -F /dev/ttyUSB<port#> clocal
38 > WtpDownload_linux -P UART -C <port#> -E -B TIM_ATF.bin -I wtmi_h.bin -I boot-image_h.bin
40 After that immediately start terminal on ``/dev/ttyUSB<port#>`` to see boot output.
67 > mox-imager -D /dev/ttyUSB<port#> -E -b 6000000 -t flash-image.bin
75 > mox-imager -D /dev/ttyUSB<port#> -E -b 6000000 -t TIM_ATF.bin wtmi_h.bin boot-image_h.bin
/rk3399_ARM-atf/docs/about/
H A Dmaintainers.rst87 Armv7-A architecture port
543 Allwinner ARMv8 platform port
553 Amlogic Meson S905 (GXBB) platform port
561 Amlogic Meson S905x (GXL) platform port
568 Amlogic Meson S905X2 (G12A) platform port
575 Amlogic Meson A113D (AXG) platform port
582 Arm FPGA platform port
590 Arm FVP Platform port
600 Arm Juno Platform port
639 Arm Total Compute platform port
[all …]
/rk3399_ARM-atf/docs/plat/arm/arm_fpga/
H A Dindex.rst7 this port ignores any power management features of the platform.
15 As a result this port is a fairly generic BL31-only port, which can serve
16 as a template for a minimal new (and possibly DT-based) platform port.
18 The aim of this port is to support as many FPGA images as possible with
/rk3399_ARM-atf/plat/allwinner/common/include/
H A Dsunxi_private.h49 void sunxi_set_gpio_out(char port, int pin, bool level_high);
/rk3399_ARM-atf/plat/mediatek/drivers/emi/
H A Demi_stub.c74 enum mtk_bl31_status slc_parity_select(unsigned int id, unsigned int port) in slc_parity_select() argument
/rk3399_ARM-atf/docs/plat/qti/
H A Dmsm8916.rst3 The MSM8916 platform port in TF-A supports multiple similar Qualcomm SoCs:
27 Unlike the :doc:`QTI SC7180/SC7280 <chrome>` ports, this port does
34 The TF-A port is much more minimal compared to the original firmware and
41 This port is **not secure**. There is no special secure memory and the
46 The port is primarily intended as a minimal PSCI implementation (without a
119 directly after BL31. For testing only, the port is primarily intended as

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