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Searched refs:pllxcfgr2 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c742 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; in clk_get_pll_fvco() local
748 fbdiv = (mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FBDIV_MASK) >> in clk_get_pll_fvco()
750 refdiv = mmio_read_32(pllxcfgr2) & RCC_PLLxCFGR2_FREFDIV_MASK; in clk_get_pll_fvco()
1630 uintptr_t pllxcfgr2 = pllxcfgr1 + RCC_OFFSET_PLLXCFGR2; in clk_stm32_pll_config_output() local
1674 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FBDIV_MASK, in clk_stm32_pll_config_output()
1677 mmio_clrsetbits_32(pllxcfgr2, RCC_PLLxCFGR2_FREFDIV_MASK, in clk_stm32_pll_config_output()
H A Dstm32mp1_clk.c501 uint16_t pllxcfgr2; member
573 .pllxcfgr2 = (off3), \
1093 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); in stm32mp1_read_pll_freq()
1788 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { in stm32mp1_check_pll_conf()
1867 mmio_write_32(rcc_base + pll->pllxcfgr2, value); in stm32mp1_pll_config_output()