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Searched refs:pll_base (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp13.c1238 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_vco() local
1247 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value); in clk_stm32_pll_config_vco()
1250 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0); in clk_stm32_pll_config_vco()
1253 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT); in clk_stm32_pll_config_vco()
1254 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE); in clk_stm32_pll_config_vco()
1261 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_csg() local
1279 mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value); in clk_stm32_pll_config_csg()
1280 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL); in clk_stm32_pll_config_csg()
1286 uintptr_t pll_base = priv->base + pll->reg_pllxcr; in clk_stm32_pll_config_out() local
1291 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value); in clk_stm32_pll_config_out()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c855 static inline void pm_pll_wait_lock(uint32_t pll_base, uint32_t pll_id) in pm_pll_wait_lock() argument
860 if (mmio_read_32(pll_base + PLL_CON(1)) & in pm_pll_wait_lock()
884 uint32_t pll_base; in pll_suspend() local
887 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_suspend()
889 pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0); in pll_suspend()
894 mmio_read_32(pll_base + PLL_CON(i)); in pll_suspend()
902 uint32_t mode, pll_base; in pll_resume() local
905 pll_base = CRU_BASE + CRU_PLL_CONS(pll_id, 0); in pll_resume()
908 pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0); in pll_resume()
914 pm_pll_wait_lock(pll_base, pll_id); in pll_resume()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpm_pd_regs.c162 static void pm_pll_wait_lock(uint32_t pll_base) in pm_pll_wait_lock() argument
166 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) in pm_pll_wait_lock()
170 if ((mmio_read_32(pll_base + CRU_PLL_CON(6)) & CRU_PLLCON6_LOCK_STATUS) != 0) in pm_pll_wait_lock()
176 ERROR("Can't wait pll(0x%x) lock\n", pll_base); in pm_pll_wait_lock()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c1392 void pm_pll_wait_lock(uint32_t pll_base) in pm_pll_wait_lock() argument
1396 if ((mmio_read_32(pll_base + CRU_PLL_CON(1)) & CRU_PLLCON1_PWRDOWN) != 0) in pm_pll_wait_lock()
1400 if (mmio_read_32(pll_base + CRU_PLL_CON(6)) & in pm_pll_wait_lock()
1407 ERROR("Can't wait pll(0x%x) lock\n", pll_base); in pm_pll_wait_lock()
H A Dpmu.h588 void pm_pll_wait_lock(uint32_t pll_base);
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_drv.c377 static bool is_pll_enabled(uintptr_t pll_base) in is_pll_enabled() argument
381 pllcr = mmio_read_32(PLLDIG_PLLCR(pll_base)); in is_pll_enabled()
382 pllsr = mmio_read_32(PLLDIG_PLLSR(pll_base)); in is_pll_enabled()