1238 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_vco()  local
1247 	mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value);  in clk_stm32_pll_config_vco()
1250 	mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0);  in clk_stm32_pll_config_vco()
1253 	mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT);  in clk_stm32_pll_config_vco()
1254 	mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE);  in clk_stm32_pll_config_vco()
1261 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_csg()  local
1279 	mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value);  in clk_stm32_pll_config_csg()
1280 	mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL);  in clk_stm32_pll_config_csg()
1286 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_config_out()  local
1291 	mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value);  in clk_stm32_pll_config_out()
1421 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_is_enabled()  local
1423 	return ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLON) != 0U);  in _clk_stm32_pll_is_enabled()
1428 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_set_on()  local
1431 	mmio_clrsetbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN,  in _clk_stm32_pll_set_on()
1437 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_set_off()  local
1440 	mmio_clrbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);  in _clk_stm32_pll_set_off()
1443 	mmio_clrbits_32(pll_base, RCC_PLLNCR_PLLON);  in _clk_stm32_pll_set_off()
1449 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_wait_ready_on()  local
1453 	while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) {  in _clk_stm32_pll_wait_ready_on()
1456 			      pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));  in _clk_stm32_pll_wait_ready_on()
1467 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_wait_ready_off()  local
1471 	while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) {  in _clk_stm32_pll_wait_ready_off()
1474 			      pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base));  in _clk_stm32_pll_wait_ready_off()
1512 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in _clk_stm32_pll_init()  local
1525 		mmio_setbits_32(pll_base,  in _clk_stm32_pll_init()
1543 	mmio_setbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN);  in _clk_stm32_pll_init()
1705 	uintptr_t pll_base = priv->base + pll->reg_pllxcr;  in clk_stm32_pll_recalc_rate()  local
1709 	cfgr1 = mmio_read_32(pll_base + RCC_OFFSET_PLLXCFGR1);  in clk_stm32_pll_recalc_rate()
1710 	fracr = mmio_read_32(pll_base + RCC_OFFSET_PLLXFRACR);  in clk_stm32_pll_recalc_rate()