Searched refs:gate (Results 1 – 5 of 5) sorted by relevance
193 const struct gate_cfg *gate = &priv->gates[gate_id]; in _clk_stm32_gate_disable() local194 uintptr_t addr = priv->base + gate->offset; in _clk_stm32_gate_disable()196 if (gate->set_clr != 0U) { in _clk_stm32_gate_disable()197 mmio_write_32(addr + RCC_MP_ENCLRR_OFFSET, BIT(gate->bit_idx)); in _clk_stm32_gate_disable()199 mmio_clrbits_32(addr, BIT(gate->bit_idx)); in _clk_stm32_gate_disable()205 const struct gate_cfg *gate = &priv->gates[gate_id]; in _clk_stm32_gate_enable() local206 uintptr_t addr = priv->base + gate->offset; in _clk_stm32_gate_enable()208 if (gate->set_clr != 0U) { in _clk_stm32_gate_enable()209 mmio_write_32(addr, BIT(gate->bit_idx)); in _clk_stm32_gate_enable()212 mmio_setbits_32(addr, BIT(gate->bit_idx)); in _clk_stm32_gate_enable()[all …]
898 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) in gate_is_non_secure() argument900 return gate->secure == N_S; in gate_is_non_secure()1304 static void __clk_enable(struct stm32mp1_clk_gate const *gate) in __clk_enable() argument1308 VERBOSE("Enable clock %u\n", gate->index); in __clk_enable()1310 if (gate->set_clr != 0U) { in __clk_enable()1311 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); in __clk_enable()1313 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); in __clk_enable()1317 static void __clk_disable(struct stm32mp1_clk_gate const *gate) in __clk_disable() argument1321 VERBOSE("Disable clock %u\n", gate->index); in __clk_disable()1323 if (gate->set_clr != 0U) { in __clk_disable()[all …]
117 /* Test chip gate configuration */
33 Checkpatch errors will gate upstream merging of pull requests.34 Checkpatch warnings will not gate merging but should be reviewed and fixed if
3505 …- don't gate/ungate an oscillator if it is not wired ([f2aebab](https://review.trustedfirmware.org…8033 …- define secure and non-secure gate clocks ([aaa09b7](https://review.trustedfirmware.org/plugins/g…10028 - Filter errors related to clock gate permissions