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Searched refs:divider (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_delay_timer.c41 uint32_t divider = plat_get_syscnt_freq2(); in tegra_delay_timer_init() local
44 while (((multiplier % 10U) == 0U) && ((divider % 10U) == 0U)) { in tegra_delay_timer_init()
46 divider /= 10U; in tegra_delay_timer_init()
55 tegra_timer_ops.clk_div = divider; in tegra_delay_timer_init()
/rk3399_ARM-atf/plat/arm/board/arm_fpga/
H A Dfpga_bl31_setup.c146 static unsigned int pl011_freq_from_divider(unsigned int divider) in pl011_freq_from_divider() argument
150 freq = divider * FPGA_DEFAULT_BAUDRATE * PL011_OVERSAMPLING; in pl011_freq_from_divider()
183 unsigned int divider; in fpga_get_system_frequency() local
188 divider = mmio_read_32(pl011_base + UARTIBRD); in fpga_get_system_frequency()
189 divider <<= PL011_FRAC_SHIFT; in fpga_get_system_frequency()
190 divider += mmio_read_32(pl011_base + UARTFBRD); in fpga_get_system_frequency()
196 return round_multiple(pl011_freq_from_divider(divider), in fpga_get_system_frequency()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.c730 const struct div_cfg *divider = &priv->div[div_id]; in clk_stm32_div_get_value() local
733 val = mmio_read_32(priv->base + divider->offset) >> divider->shift; in clk_stm32_div_get_value()
734 val &= clk_div_mask(divider->width); in clk_stm32_div_get_value()
743 const struct div_cfg *divider = &priv->div[div_id]; in _clk_stm32_divider_recalc() local
747 div = _get_div(divider->table, val, divider->flags, divider->width); in _clk_stm32_divider_recalc()
770 const struct div_cfg *divider; in clk_stm32_set_div() local
779 divider = &priv->div[div_id]; in clk_stm32_set_div()
780 address = priv->base + divider->offset; in clk_stm32_set_div()
782 mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); in clk_stm32_set_div()
783 mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask); in clk_stm32_set_div()
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H A Dstm32mp1_clk.c269 const struct div_cfg *divider; in clk_stm32_set_div() local
278 divider = &priv->div[div_id]; in clk_stm32_set_div()
279 address = priv->base + divider->offset; in clk_stm32_set_div()
281 mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); in clk_stm32_set_div()
282 mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask); in clk_stm32_set_div()
284 if (divider->bitrdy == DIV_NO_BIT_RDY) { in clk_stm32_set_div()
289 mask = BIT(divider->bitrdy); in clk_stm32_set_div()
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dzynqmp_pm_api_sys.c1326 uint32_t divider, in pm_clock_setdivider() argument
1340 status = pm_pll_set_parameter(nid, PM_PLL_PARAM_FBDIV, divider, in pm_clock_setdivider()
1351 if (div0 == (divider & div0)) { in pm_clock_setdivider()
1353 val = divider & ~div0; in pm_clock_setdivider()
1354 } else if (div1 == (divider & div1)) { in pm_clock_setdivider()
1356 val = (divider & ~div1) >> 16; in pm_clock_setdivider()
1384 uint32_t *divider, in pm_clock_getdivider() argument
1395 status = pm_pll_get_parameter(nid, PM_PLL_PARAM_FBDIV, divider, in pm_clock_getdivider()
1414 *divider = val; in pm_clock_getdivider()
1425 *divider |= val << 16; in pm_clock_getdivider()
H A Dzynqmp_pm_api_sys.h153 uint32_t divider, uint32_t flag);
155 uint32_t *divider, uint32_t flag);
/rk3399_ARM-atf/docs/
H A Dchange-log.md1878 …- get MC_CGM divider's parent ([1586904](https://review.trustedfirmware.org/plugins/gitiles/TF-A/t…
1879 …- get MC_CGM divider's rate ([ad412c0](https://review.trustedfirmware.org/plugins/gitiles/TF-A/tru…
1883 …- set MC_CGM divider's rate ([f99078a](https://review.trustedfirmware.org/plugins/gitiles/TF-A/tru…
3493 …- set rate for clock fixed divider ([65739db](https://review.trustedfirmware.org/plugins/gitiles/T…
3495 …- set rate for PLL divider objects ([de950ef](https://review.trustedfirmware.org/plugins/gitiles/T…
6224 …- implement timer init divider via CPU frequency for N5X ([02a9d70](https://review.trustedfirmware…
7538 …- implement timer init divider via cpu frequency. ([#1](https://review.trustedfirmware.org:29418/T…