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Searched refs:clk_src (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_drv.c460 unsigned int clk_src, ldepth = depth; in enable_pll() local
510 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); in enable_pll()
512 if ((clk_src == sclk_id) && pll_enabled && in enable_pll()
1586 unsigned long prate, clk_src; in get_pll_freq() local
1609 clk_src = mmio_read_32(PLLDIG_PLLCLKMUX(pll_addr)); in get_pll_freq()
1610 switch (clk_src) { in get_pll_freq()
1612 clk_src = S32CC_CLK_FIRC; in get_pll_freq()
1615 clk_src = S32CC_CLK_FXOSC; in get_pll_freq()
1618 ERROR("Failed to identify PLL source id %" PRIu64 "\n", clk_src); in get_pll_freq()
1622 source = s32cc_get_arch_clk(clk_src); in get_pll_freq()
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c1939 static void flexclkgen_config_channel(uint16_t channel, unsigned int clk_src, in flexclkgen_config_channel() argument
1975 clk_src); in flexclkgen_config_channel()
1992 unsigned int channel, clk_src, pdiv, fdiv; in stm32mp2_clk_flexgen_configure() local
2002 clk_src = (cmd_data & FLEX_SEL_MASK) >> FLEX_SEL_SHIFT; in stm32mp2_clk_flexgen_configure()
2011 flexclkgen_config_channel(channel, clk_src, pdiv, fdiv); in stm32mp2_clk_flexgen_configure()
/rk3399_ARM-atf/drivers/marvell/comphy/
H A Dphy-comphy-cp110.c1264 _Bool clk_src = COMPHY_GET_CLK_SRC(comphy_mode); in mvebu_cp110_comphy_pcie_power_on() local
1351 if (clk_dir && clk_src && (comphy_index == COMPHY_LANE5)) { in mvebu_cp110_comphy_pcie_power_on()