Searched refs:clk_set_rate (Results 1 – 3 of 3) sorted by relevance
| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/ |
| H A D | s32cc_early_clks.c | 32 ret = clk_set_rate(S32CC_CLK_FXOSC, S32CC_FXOSC_FREQ, NULL); in setup_fxosc()
49 ret = clk_set_rate(S32CC_CLK_ARM_PLL_VCO, S32CC_ARM_PLL_VCO_FREQ, NULL); in setup_arm_pll()
54 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); in setup_arm_pll()
71 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_VCO, S32CC_PERIPH_PLL_VCO_FREQ, NULL); in setup_periph_pll()
76 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_PHI3, S32CC_PERIPH_PLL_PHI3_FREQ, NULL); in setup_periph_pll()
93 ret = clk_set_rate(S32CC_CLK_A53_CORE, S32CC_A53_FREQ, NULL); in enable_a53_clk()
115 ret = clk_set_rate(S32CC_CLK_XBAR_2X, S32CC_XBAR_2X_FREQ, NULL); in enable_xbar_clk()
159 ret = clk_set_rate(S32CC_CLK_DDR_PLL_VCO, S32CC_DDR_PLL_VCO_FREQ, NULL); in setup_ddr_pll()
164 ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL); in setup_ddr_pll()
199 ret = clk_set_rate(S32CC_CLK_PERIPH_PLL_DFS3, in enable_usdhc_clk()
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| /rk3399_ARM-atf/include/drivers/ |
| H A D | clk.h | 27 int clk_set_rate(unsigned long id, unsigned long rate, unsigned long *orate);
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| /rk3399_ARM-atf/drivers/clk/ |
| H A D | clk.c | 37 int clk_set_rate(unsigned long id, unsigned long rate, unsigned long *orate) in clk_set_rate() function
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