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Searched refs:bl2_tzram_layout (Results 1 – 11 of 11) sorted by relevance

/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl1_plat_setup.c30 static meminfo_t bl2_tzram_layout; variable
56 bl2_tzram_layout.total_base = BL2_BASE; in bl1_plat_handle_post_image_load()
57 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE; in bl1_plat_handle_post_image_load()
59 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t)); in bl1_plat_handle_post_image_load()
61 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout; in bl1_plat_handle_post_image_load()
64 (void *)&bl2_tzram_layout); in bl1_plat_handle_post_image_load()
H A Dbl2_plat_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
186 bl2_tzram_layout = *mem_layout; in bl2_early_platform_setup2()
200 plat_configure_mmu_el1(bl2_tzram_layout.total_base, in bl2_plat_arch_setup()
201 bl2_tzram_layout.total_size, in bl2_plat_arch_setup()
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_bl2_setup.c27 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
37 return &bl2_tzram_layout; in bl2_plat_sec_mem_layout()
52 bl2_tzram_layout = *mem_layout; in marvell_bl2_early_platform_setup()
79 marvell_setup_page_tables(bl2_tzram_layout.total_base, in marvell_bl2_plat_arch_setup()
80 bl2_tzram_layout.total_size, in marvell_bl2_plat_arch_setup()
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_bl2_setup.c22 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
54 bl2_tzram_layout = *mem_layout; in bcm_bl2_early_platform_setup()
102 MAP_REGION_FLAT(bl2_tzram_layout.total_base, in bcm_bl2_plat_arch_setup()
103 bl2_tzram_layout.total_size, in bcm_bl2_plat_arch_setup()
/rk3399_ARM-atf/plat/rpi/rpi3/
H A Drpi3_bl2_setup.c28 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
78 bl2_tzram_layout = *mem_layout; in bl2_early_platform_setup2()
103 rpi3_setup_page_tables(bl2_tzram_layout.total_base, in bl2_plat_arch_setup()
104 bl2_tzram_layout.total_size, in bl2_plat_arch_setup()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_bl2_setup.c33 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
90 bl2_tzram_layout.total_base, \
91 bl2_tzram_layout.total_size, \
118 bl2_tzram_layout.total_base = ARM_BL_RAM_BASE; in arm_bl2_early_platform_setup()
119 bl2_tzram_layout.total_size = ARM_BL_RAM_SIZE; in arm_bl2_early_platform_setup()
127 bl2_tzram_layout = *(meminfo_t *)transfer_list_entry_data(te); in arm_bl2_early_platform_setup()
133 bl2_tzram_layout = *(meminfo_t *)arg1; in arm_bl2_early_platform_setup()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl2_setup.c34 static meminfo_t bl2_tzram_layout; variable
277 bl2_tzram_layout.total_base = BL2_RW_BASE; in bl2_early_platform_setup2()
278 bl2_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; in bl2_early_platform_setup2()
283 hikey_init_mmu_el3(bl2_tzram_layout.total_base, in bl2_plat_arch_setup()
284 bl2_tzram_layout.total_size, in bl2_plat_arch_setup()
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_bl2_setup.c37 static meminfo_t bl2_tzram_layout; variable
302 bl2_tzram_layout.total_base = BL2_RW_BASE; in bl2_early_platform_setup2()
303 bl2_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE; in bl2_early_platform_setup2()
308 hikey960_init_mmu_el3(bl2_tzram_layout.total_base, in bl2_plat_arch_setup()
309 bl2_tzram_layout.total_size, in bl2_plat_arch_setup()
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_bl2_setup.c31 bl2_tzram_layout.total_base, \
32 bl2_tzram_layout.total_size, \
54 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
66 bl2_tzram_layout = *mem_layout; in bl2_early_platform_setup2()
/rk3399_ARM-atf/plat/renesas/rzg/
H A Dbl2_plat_setup.c109 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
424 return &bl2_tzram_layout; in bl2_plat_sec_mem_layout()
868 bl2_tzram_layout.total_base = BL31_BASE; in bl2_early_platform_setup2()
869 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; in bl2_early_platform_setup2()
/rk3399_ARM-atf/plat/renesas/rcar/
H A Dbl2_plat_setup.c115 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
645 return &bl2_tzram_layout; in bl2_plat_sec_mem_layout()
1257 bl2_tzram_layout.total_base = BL31_BASE; in bl2_early_platform_setup2()
1258 bl2_tzram_layout.total_size = BL31_LIMIT - BL31_BASE; in bl2_early_platform_setup2()