| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/constraints/ |
| H A D | mt_spm_trace.h | 69 #define MT_SPM_TRACE_COMMON_U32_WR(_type, _val) \ argument
73 _val); \
83 #define MT_SPM_TRACE_COMMON_U32_RD(_type, _val) \ argument
87 _val); \
90 #define MT_SPM_TRACE_COMMON_RD(_type, _val) \ argument
92 int ret = MT_SPM_SYSRAM_R(MT_SPM_SYSRAM_COMMON, _type, _val); \
97 #define MT_SPM_TRACE_SUSPEND_U32_WR(_type, _val) \ argument
101 _val); \
104 #define MT_SPM_TRACE_SUSPEND_WR(_type, _val, _sz) \ argument
106 int ret = MT_SPM_SYSRAM_W(MT_SPM_SYSRAM_SUSPEND, _type, _val, \
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/constraints/ |
| H A D | mt_spm_trace.h | 69 #define MT_SPM_TRACE_COMMON_U32_WR(_type, _val) ({ \ argument
71 MT_SPM_SYSRAM_SLOT(_type)), _val); })
77 #define MT_SPM_TRACE_COMMON_U32_RD(_type, _val) ({ \ argument
79 MT_SPM_SYSRAM_SLOT(_type)), _val); })
81 #define MT_SPM_TRACE_COMMON_RD(_type, _val) ({ \ argument
83 _type, _val); ret; })
86 #define MT_SPM_TRACE_SUSPEND_U32_WR(_type, _val) ({ \ argument
88 MT_SPM_SYSRAM_SLOT(_type)), _val); })
90 #define MT_SPM_TRACE_SUSPEND_WR(_type, _val, _sz) ({ \ argument
92 _type, _val, _sz); ret; })
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| /rk3399_ARM-atf/include/arch/aarch32/ |
| H A D | asm_macros.S | 135 .macro mov_imm _reg, _val argument
136 .if ((\_val) & 0xffff0000) == 0
137 mov \_reg, #(\_val)
139 movw \_reg, #((\_val) & 0xffff)
140 movt \_reg, #((\_val) >> 16)
181 .macro orr64_imm _reg_l, _reg_h, _val argument
182 .if (\_val >> 32)
183 orr \_reg_h, \_reg_h, #(\_val >> 32)
185 .if (\_val & 0xffffffff)
186 orr \_reg_l, \_reg_l, #(\_val & 0xffffffff)
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/ |
| H A D | mt_cpu_pm.h | 63 #define PER_CLUSTER_PWR_CTRL(_val, _cl) ({ \ argument
66 PER_CLUSTER_PWR_DATA(_val, 0); \
81 #define PER_CPU_PWR_CTRL(_val, _cpu) ({ \ argument
84 PER_CPU_PWR_DATA(_val, 0, 0); \
87 PER_CPU_PWR_DATA(_val, 0, 1); \
90 PER_CPU_PWR_DATA(_val, 0, 2); \
93 PER_CPU_PWR_DATA(_val, 0, 3); \
96 PER_CPU_PWR_DATA(_val, 0, 4); \
99 PER_CPU_PWR_DATA(_val, 0, 5); \
102 PER_CPU_PWR_DATA(_val, 0, 6); \
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | asm_macros.S | 170 .macro _mov_imm16 _reg, _val, _shift
171 .if (\_val >> \_shift) & 0xffff
172 .if (\_val & (1 << \_shift - 1))
173 movk \_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
175 mov \_reg, \_val & (0xffff << \_shift)
186 .macro mov_imm _reg, _val argument
187 .if (\_val) == 0
190 _mov_imm16 \_reg, (\_val), 0
191 _mov_imm16 \_reg, (\_val), 16
192 _mov_imm16 \_reg, (\_val), 32
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| /rk3399_ARM-atf/plat/arm/board/juno/aarch64/ |
| H A D | juno_helpers.S | 228 .macro emit_movw _reg_d, _val argument
230 ((\_val & 0xfff) | \
231 ((\_val & 0xf000) << 4)))
238 .macro emit_movt _reg_d, _val argument
240 (((\_val & 0x0fff0000) >> 16) | \
241 ((\_val & 0xf0000000) >> 12)))
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/include/ |
| H A D | agilex5_iossm_mailbox.h | 23 #define FIELD_PREP(_mask, _val) \ argument
25 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
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| /rk3399_ARM-atf/include/drivers/cadence/ |
| H A D | cdns_nand.h | 20 #define FIELD_PREP(_mask, _val) \ argument
22 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
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| /rk3399_ARM-atf/plat/intel/soc/common/drivers/ccu/ |
| H A D | ncore_ccu.c | 35 #define FIELD_PREP(_mask, _val) \ argument
37 ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
|