| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | gicv5.h | 95 #define DEFINE_GICV5_MMIO_WRITE_FUNC(_name, _offset) \ argument
98 mmio_write_32(base + _offset, val); \
101 #define DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset) \ argument
104 return mmio_read_32(base + _offset); \
107 #define DEFINE_GICV5_MMIO_WRITE_INDEXED_FUNC(_name, _offset) \ argument
110 mmio_write_32(base + _offset + (index * sizeof(uint32_t)), val); \
113 #define DEFINE_GICV5_MMIO_READ_INDEXED_FUNC(_name, _offset) \ argument
116 return mmio_read_32(base + _offset + (index * sizeof(uint32_t))); \
119 #define DEFINE_GICV5_MMIO_RW_FUNCS(_name, _offset) \ argument
120 DEFINE_GICV5_MMIO_READ_FUNC(_name, _offset) \
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| /rk3399_ARM-atf/include/services/ |
| H A D | rmmd_svc.h | 22 #define SMC64_RMI_FID(_offset) \ argument
26 (((RMI_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \
71 #define SMC64_RMMD_EL3_FID(_offset) \ argument
75 (((RMMD_EL3_FNUM_MIN_VALUE + (_offset)) & FUNCID_NUM_MASK) \
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| /rk3399_ARM-atf/plat/mediatek/drivers/gpio/ |
| H A D | mtgpio_common.h | 91 #define PIN(_id, _flag, _bit, _base, _offset) { \ argument
96 .offset = _offset, \
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32-core.h | 269 #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ argument
275 .offset = (_offset),\
321 #define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\ argument
322 .offset = (_offset),\
327 #define CSS(_offset, _bit_css) &(struct stm32_clk_css){\ argument
328 .offset = (_offset),\
332 #define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\ argument
333 .offset = (_offset),\
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| H A D | clk-stm32mp13.c | 379 #define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\ argument
383 .offset = (_offset),\
390 #define MUX_RDY_CFG(id, src, _offset, _shift, _witdh)[id] = {\ argument
394 .offset = (_offset),\
601 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ argument
602 .offset = (_offset),\
777 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ argument
778 .offset = _offset,\
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| H A D | clk-stm32mp2.c | 323 #define MUX_CONF(id, src, _offset, _shift, _witdh)[id] = {\ argument
327 .offset = (_offset),\
475 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ argument
476 .offset = (_offset),\
614 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ argument
615 .offset = _offset,\
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| H A D | stm32mp1_clk.c | 123 #define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\ argument
125 .offset = (_offset),\
153 #define MUXRDY_CFG(_id, _offset, _shift, _width, _bitrdy)\ argument
155 .offset = (_offset),\
161 #define MUX_CFG(_id, _offset, _shift, _width)\ argument
162 MUXRDY_CFG(_id, _offset, _shift, _width, MUX_NO_BIT_RDY)
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/ |
| H A D | mt_spm_common_v1.h | 35 #define DECLARE_PERI_REQ_EN_REG(_offset, _info) \ argument
36 ({ _info.req_en = REG_PERI_REQ_EN(_offset); })
38 #define DECLARE_PERI_REQ_STA_REG(_offset, _info) \ argument
39 ({ _info.req_sta = REG_PERI_REQ_STA(_offset); })
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