Searched refs:TEGRA_SE0_BASE (Results 1 – 8 of 8) sorted by relevance
92 return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset)); in tegra_se_read_32()97 mmio_write_32(((uint32_t)(TEGRA_SE0_BASE + offset)), val); in tegra_se_write_32()
157 return mmio_read_32((uint32_t)(TEGRA_SE0_BASE + offset)); in tegra_se_read_32()162 mmio_write_32((uint32_t)(TEGRA_SE0_BASE + offset), val); in tegra_se_write_32()
465 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT); in tegra_se_suspend()466 se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL); in tegra_se_suspend()503 mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]); in tegra_se_resume()504 mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]); in tegra_se_resume()
130 se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + in tegra_soc_pwr_domain_suspend()411 mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT, in tegra_soc_pwr_domain_on_finish()
91 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
221 #define TEGRA_SE0_BASE U(0x03AC0000) macro
181 #define TEGRA_SE0_BASE U(0x03AC0000) macro
111 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x1000U, /* 4KB */