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Searched refs:TEGRA_MC_BASE (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/nvidia/tegra/include/drivers/
H A Dmemctrl_v2.h40 .reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
64 return mmio_read_32(TEGRA_MC_BASE + off); in tegra_mc_read_32()
69 mmio_write_32(TEGRA_MC_BASE + off, val); in tegra_mc_write_32()
H A Dmemctrl_v1.h49 return mmio_read_32(TEGRA_MC_BASE + off); in tegra_mc_read_32()
54 mmio_write_32(TEGRA_MC_BASE + off, val); in tegra_mc_write_32()
/rk3399_ARM-atf/plat/nvidia/tegra/drivers/memctrl/
H A Dmemctrl_v1.c206 mcerr = mmio_read_32(TEGRA_MC_BASE + MC_INTSTATUS); in tegra_memctrl_clear_pending_interrupts()
210 mmio_write_32((TEGRA_MC_BASE + MC_INTSTATUS), mcerr); in tegra_memctrl_clear_pending_interrupts()
/rk3399_ARM-atf/plat/nvidia/tegra/common/
H A Dtegra_sip_calls.c56 if (mmio_read_32(TEGRA_MC_BASE + MC_VIDEO_PROTECT_REG_CTRL) in tegra_sip_handler()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_trampoline.S134 mov x0, #TEGRA_MC_BASE
H A Dplat_setup.c95 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x8000U, /* 32KB */
/rk3399_ARM-atf/plat/nvidia/tegra/include/t194/
H A Dtegra_def.h82 #define TEGRA_MC_BASE U(0x02C10000) macro