121f1fd95SVarun Wadekar /* 250e91633SAnthony Zhou * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 321f1fd95SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 521f1fd95SVarun Wadekar */ 621f1fd95SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef MEMCTRL_V1_H 8c3cf06f1SAntonio Nino Diaz #define MEMCTRL_V1_H 921f1fd95SVarun Wadekar 10*09d40e0eSAntonio Nino Diaz #include <lib/mmio.h> 11*09d40e0eSAntonio Nino Diaz 1221f1fd95SVarun Wadekar #include <tegra_def.h> 1321f1fd95SVarun Wadekar 1421f1fd95SVarun Wadekar /* SMMU registers */ 1550e91633SAnthony Zhou #define MC_SMMU_CONFIG_0 0x10U 1650e91633SAnthony Zhou #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U 1750e91633SAnthony Zhou #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U 1850e91633SAnthony Zhou #define MC_SMMU_TLB_CONFIG_0 0x14U 1950e91633SAnthony Zhou #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U 2050e91633SAnthony Zhou #define MC_SMMU_PTC_CONFIG_0 0x18U 2150e91633SAnthony Zhou #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU 2250e91633SAnthony Zhou #define MC_SMMU_TLB_FLUSH_0 0x30U 2350e91633SAnthony Zhou #define TLB_FLUSH_VA_MATCH_ALL 0U 2450e91633SAnthony Zhou #define TLB_FLUSH_ASID_MATCH_DISABLE 0U 2550e91633SAnthony Zhou #define TLB_FLUSH_ASID_MATCH_SHIFT 31U 2621f1fd95SVarun Wadekar #define MC_SMMU_TLB_FLUSH_ALL \ 2721f1fd95SVarun Wadekar (TLB_FLUSH_VA_MATCH_ALL | \ 2821f1fd95SVarun Wadekar (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 2950e91633SAnthony Zhou #define MC_SMMU_PTC_FLUSH_0 0x34U 3050e91633SAnthony Zhou #define MC_SMMU_PTC_FLUSH_ALL 0U 3150e91633SAnthony Zhou #define MC_SMMU_ASID_SECURITY_0 0x38U 3250e91633SAnthony Zhou #define MC_SMMU_ASID_SECURITY 0U 3350e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U 3450e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU 3550e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U 3650e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U 3750e91633SAnthony Zhou #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U 3821f1fd95SVarun Wadekar #define MC_SMMU_TRANSLATION_ENABLE (~0) 3921f1fd95SVarun Wadekar 400c2276e3SVarun Wadekar /* MC IRAM aperture registers */ 410c2276e3SVarun Wadekar #define MC_IRAM_BASE_LO 0x65CU 420c2276e3SVarun Wadekar #define MC_IRAM_TOP_LO 0x660U 430c2276e3SVarun Wadekar #define MC_IRAM_BASE_TOP_HI 0x980U 440c2276e3SVarun Wadekar #define MC_IRAM_REG_CTRL 0x964U 450c2276e3SVarun Wadekar #define MC_DISABLE_IRAM_CFG_WRITES 1U 460c2276e3SVarun Wadekar tegra_mc_read_32(uint32_t off)4721f1fd95SVarun Wadekarstatic inline uint32_t tegra_mc_read_32(uint32_t off) 4821f1fd95SVarun Wadekar { 4921f1fd95SVarun Wadekar return mmio_read_32(TEGRA_MC_BASE + off); 5021f1fd95SVarun Wadekar } 5121f1fd95SVarun Wadekar tegra_mc_write_32(uint32_t off,uint32_t val)5221f1fd95SVarun Wadekarstatic inline void tegra_mc_write_32(uint32_t off, uint32_t val) 5321f1fd95SVarun Wadekar { 5421f1fd95SVarun Wadekar mmio_write_32(TEGRA_MC_BASE + off, val); 5521f1fd95SVarun Wadekar } 5621f1fd95SVarun Wadekar 57c3cf06f1SAntonio Nino Diaz #endif /* MEMCTRL_V1_H */ 58