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Searched refs:SYSMGR_USB3_MISC0_PORT_OVR_CURR_PIPE_PWR (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_system_manager.h233 #define SYSMGR_USB3_MISC0_PORT_OVR_CURR_PIPE_PWR BIT(14) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c165 reg_val |= SYSMGR_USB3_MISC0_PORT_OVR_CURR_PIPE_PWR; /* set pipe power present bit */ in bl2_early_platform_setup2()