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Searched refs:SYSCFG_BASE (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_syscfg.c126 while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) { in enable_io_comp_cell_finish()
134 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL); in enable_io_comp_cell_finish()
141 if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) || in disable_io_comp_cell()
142 ((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) & in disable_io_comp_cell()
147 value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT; in disable_io_comp_cell()
149 mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC); in disable_io_comp_cell()
152 value |= mmio_read_32(SYSCFG_BASE + cmpcr_off); in disable_io_comp_cell()
154 mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL); in disable_io_comp_cell()
156 mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN); in disable_io_comp_cell()
240 mmio_write_32(SYSCFG_BASE + SYSCFG_HSLVEN0R + reg_offset, HSLV_KEY); in enable_hslv_by_index()
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H A Dstm32mp1_def.h611 #define SYSCFG_BASE U(0x50020000) macro
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dstm32mp2_syscfg.c30 return mmio_read_32(SYSCFG_BASE + SYSCFG_DEVICEID) & SYSCFG_DEVICEID_DEV_ID_MASK; in stm32mp_syscfg_get_chip_dev_id()
H A Dstm32mp2_def.h441 #define SYSCFG_BASE U(0x44230000) macro