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Searched refs:STIMER1_BASE (Results 1 – 8 of 8) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/secure/
H A Dsecure.c94 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in sram_secure_timer_init()
96 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); in sram_secure_timer_init()
97 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff); in sram_secure_timer_init()
100 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in sram_secure_timer_init()
112 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, 0); in secure_timer_init()
114 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT0, 0xffffffff); in secure_timer_init()
115 mmio_write_32(STIMER1_BASE + TIMER_LOAD_COUNT1, 0xffffffff); in secure_timer_init()
118 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
H A Dsecure.h91 #define STIMER1_BASE (STIME_BASE + 0x20) macro
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpm_pd_regs.c124 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x00, 0),
125 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x00, 0),
126 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x20, 0),
127 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x20, 0),
128 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x40, 0),
129 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x40, 0),
130 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x60, 0),
131 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x60, 0),
132 REG_REGION(0x00, 0x04, 4, STIMER1_BASE + 0x80, 0),
133 REG_REGION(0x10, 0x10, 4, STIMER1_BASE + 0x80, 0),
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.c70 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); in secure_timer_init()
71 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); in secure_timer_init()
74 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); in secure_timer_init()
H A Dsoc.h32 #define STIMER1_BASE (STIME_BASE + 0x20) macro
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h107 #define STIMER1_BASE 0x2a4b0000 macro
141 #define STIMER1_CHN_BASE(i) (STIMER1_BASE + 0x1000 * (i))
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h139 #define STIMER1_BASE 0xfed30000 macro
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/
H A Dsoc.h141 #define STIMER1_CHN_BASE(n) (STIMER1_BASE + 0x20 * (n))