Searched refs:RTX_CLK_CTL0 (Results 1 – 2 of 2) sorted by relevance
200 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF); in imx_gpc_pm_domain_enable()219 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0x0); in imx_gpc_pm_domain_enable()224 mmio_write_32(IMX_HDMI_CTL_BASE + RTX_CLK_CTL0, 0xFFFFFFFF); in imx_gpc_pm_domain_enable()
138 #define RTX_CLK_CTL0 U(0x40) macro