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Searched refs:RCC_BDCR_VSWRST (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dbl2_plat_setup.c139 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in reset_backup_domain()
141 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { in reset_backup_domain()
145 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in reset_backup_domain()
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dbl2_plat_setup.c249 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
251 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == in bl2_el3_plat_arch_setup()
256 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h351 #define RCC_BDCR_VSWRST BIT(31) macro
H A Dstm32mp15_rcc.h499 #define RCC_BDCR_VSWRST BIT(31) macro
H A Dstm32mp21_rcc.h2338 #define RCC_BDCR_VSWRST BIT(31) macro
H A Dstm32mp25_rcc.h2400 #define RCC_BDCR_VSWRST BIT(31) macro