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Searched refs:RCC_APB5DIVR (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c139 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 31),
1163 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); in get_clock_rate()
H A Dclk-stm32mp13.c804 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
H A Dclk-stm32mp2.c629 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31),
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h71 #define RCC_APB5DIVR U(0X580) macro
H A Dstm32mp15_rcc.h23 #define RCC_APB5DIVR U(0x40) macro
H A Dstm32mp21_rcc.h296 #define RCC_APB5DIVR U(0x4BC) macro