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Searched refs:PWR_BDCR1 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dbl2_plat_setup.c130 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); in reset_backup_domain()
132 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { in reset_backup_domain()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp2_pwr.h25 #define PWR_BDCR1 U(0x38) macro