Home
last modified time | relevance | path

Searched refs:MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/dcm/
H A Dmtk_dcm_utils.c84 ret &= dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm_is_on()
101 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
112 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
314 return dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm_is_on()
323 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm()
328 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm()
346 ret &= dcm_check_state(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm_is_on()
360 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
368 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
H A Dmtk_dcm_utils.h27 #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/dcm/
H A Dmtk_dcm_utils.c100 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
117 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
128 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
373 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_misc_dcm_is_on()
384 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm()
389 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm()
415 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_mp0_qdcm_is_on()
429 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
437 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_mp0_qdcm()
H A Dmtk_dcm_utils.h26 #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/dcm/
H A Dmtk_dcm_utils.c82 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_apb_dcm_is_on()
99 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
110 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_apb_dcm()
400 ret &= ((mmio_read_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0) & in dcm_mp_cpusys_top_misc_dcm_is_on()
411 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm()
416 mmio_clrsetbits_32(MP_CPUSYS_TOP_MP_MISC_DCM_CFG0, in dcm_mp_cpusys_top_misc_dcm()
H A Dmtk_dcm_utils.h30 #define MP_CPUSYS_TOP_MP_MISC_DCM_CFG0 (MP_CPUSYS_TOP_BASE + 0x2518) macro