Searched refs:EL1_EL0_REGIME (Results 1 – 9 of 9) sorted by relevance
102 tf_xlat_ctx.xlat_regime = EL1_EL0_REGIME; in init_xlat_tables()144 if (tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME) { in xlat_make_tables_readonly()156 assert(tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME); in xlat_make_tables_readonly()174 if (tf_xlat_ctx.xlat_regime == EL1_EL0_REGIME) { in xlat_make_tables_readonly()215 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); in enable_mmu_el1()258 tf_xlat_ctx.va_max_address, EL1_EL0_REGIME); in enable_mmu_svc_mon()
73 assert(xlat_regime == EL1_EL0_REGIME); in xlat_desc_print()84 uint64_t xn_mask = xlat_arch_regime_get_xn_desc(EL1_EL0_REGIME); in xlat_desc_print()228 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_tables_print()360 assert((ctx->xlat_regime == EL1_EL0_REGIME) || in xlat_get_mem_attributes_internal()416 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_get_mem_attributes_internal()
145 if (ctx->xlat_regime == EL1_EL0_REGIME) { in xlat_desc()1211 (ctx->xlat_regime == EL1_EL0_REGIME)); in init_xlat_tables_ctx()
77 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mmu_enabled_ctx()98 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_regime_get_xn_desc()114 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_tlbi_va()193 if (xlat_regime == EL1_EL0_REGIME) { in setup_mmu_cfg()
144 if (ctx->xlat_regime == EL1_EL0_REGIME) { in is_mmu_enabled_ctx()172 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_regime_get_xn_desc()196 if (xlat_regime == EL1_EL0_REGIME) { in xlat_arch_tlbi_va()294 if (xlat_regime == EL1_EL0_REGIME) { in setup_mmu_cfg()
23 EL1_EL0_REGIME, PLAT_SP_IMAGE_XLAT_SECTION_NAME,
154 #define EL1_EL0_REGIME 1 macro
616 EL1_EL0_REGIME); in spmc_el0_sp_setup_mmu()714 sp->xlat_ctx_handle->xlat_regime = EL1_EL0_REGIME; in spmc_el0_sp_setup()
227 EL1_EL0_REGIME); in spm_sp_setup()