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Searched refs:CTLR_ENABLE_G0_BIT (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicv2_main.c46 val = CTLR_ENABLE_G0_BIT | FIQ_EN_BIT | FIQ_BYP_DIS_GRP0; in gicv2_cpuif_enable()
67 val &= ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT); in gicv2_cpuif_disable()
90 if ((ctlr & CTLR_ENABLE_G0_BIT) == 0U) { in gicv2_pcpu_distif_init()
92 ctlr | CTLR_ENABLE_G0_BIT); in gicv2_pcpu_distif_init()
111 ctlr & ~(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1_BIT)); in gicv2_distif_init()
122 gicd_write_ctlr(driver_data->gicd_base, ctlr | CTLR_ENABLE_G0_BIT); in gicv2_distif_init()
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600_multichip.c71 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in set_gicd_dchipr_rt_owner()
107 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in set_gicd_chipr_n()
377 (CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1S_BIT | in gic600_multichip_init()
H A Dgicv3_helpers.c259 ctlr_enable |= CTLR_ENABLE_G0_BIT; in gicv3_secure_spis_config_props()
372 ctlr_enable |= CTLR_ENABLE_G0_BIT; in gicv3_secure_ppi_sgi_config_props()
H A Dgicv3_main.c201 CTLR_ENABLE_G0_BIT | in gicv3_distif_init()
852 CTLR_ENABLE_G0_BIT | in gicv3_distif_init_restore()
/rk3399_ARM-atf/include/drivers/arm/
H A Dgic_common.h62 #define CTLR_ENABLE_G0_BIT BIT_32(CTLR_ENABLE_G0_SHIFT) macro
/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dcm3_system_reset.c137 a3700_gicd_ctlr_clear_bits(CTLR_ENABLE_G0_BIT | CTLR_ENABLE_G1NS_BIT | in a3700_gic_reset()
/rk3399_ARM-atf/plat/imx/imx9/common/
H A Dimx9_psci_common.c296 CTLR_ENABLE_G0_BIT | in imx_system_reset()