| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/ |
| H A D | pmu.c | 255 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
256 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
266 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
517 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in ddr_suspend()
519 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in ddr_suspend()
521 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in ddr_suspend()
523 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in ddr_suspend()
534 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in dmc_restore()
536 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in dmc_restore()
538 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in dmc_restore()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/ |
| H A D | rk3399_gpio.c | 93 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
100 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
107 .clkgate_reg = CRU_BASE + CRU_CLKGATE_CON(31),
308 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)); in plat_rockchip_save_gpio()
316 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_save_gpio()
338 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_save_gpio()
360 cru_gate_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)); in plat_rockchip_restore_gpio()
368 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_restore_gpio()
384 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in plat_rockchip_restore_gpio()
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| /rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/ |
| H A D | soc.h | 63 #define CRU_CLKGATE_CON 0x200 macro
64 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4)
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/ |
| H A D | rk3588_clk.c | 1216 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), in clk_scmi_cclk_sdmmc_set_status()
1255 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), in clk_scmi_dclk_sdmmc_set_status()
1353 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(2), in clk_scmi_tclk_wdt_set_status()
1398 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), in clk_scmi_keyladder_core_set_status()
1443 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), in clk_scmi_keyladder_rng_set_status()
1613 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), in clk_scmi_crypto_rng_set_status()
1659 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(0), in clk_scmi_crypto_core_set_status()
1705 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), in clk_scmi_crypto_pka_set_status()
1759 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), in clk_scmi_hclk_sd_set_status()
1804 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(1), in clk_scmi_crypto_rng_s_set_status()
[all …]
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| /rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/ |
| H A D | soc.h | 45 #define CRU_CLKGATE_CON 0x160 macro
46 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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| /rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/ |
| H A D | soc.h | 83 #define CRU_CLKGATE_CON 0x200 macro
84 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4))
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| /rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/ |
| H A D | soc.h | 42 #define CRU_CLKGATE_CON(i) (0x200 + ((i) * 4)) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/soc/ |
| H A D | soc.h | 46 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/ |
| H A D | pmu.c | 326 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
329 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_disable()
355 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clk_gate_con_save()
378 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/ |
| H A D | soc.h | 192 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) macro
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/ |
| H A D | pmu.c | 202 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clk_gate_con_save()
210 clk_save[j] = mmio_read_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i)); in clk_gate_con_save()
218 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
226 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
234 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_restore()
245 mmio_write_32(PMU1CRU_BASE + CRU_CLKGATE_CON(i), in clk_gate_con_restore()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/ |
| H A D | pmu.c | 843 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3)); in sys_slp_config()
844 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1)); in sys_slp_config()
929 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >> in suspend_apio()
933 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in suspend_apio()
1053 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31), in resume_apio()
1446 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), in rockchip_soc_sys_pwr_dm_resume()
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| /rk3399_ARM-atf/plat/rockchip/rk3576/drivers/soc/ |
| H A D | soc.h | 37 #define CRU_CLKGATE_CON(i) ((i) * 0x4 + 0x800) macro
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