Lines Matching refs:CRU_CLKGATE_CON
255 mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clks_gating_suspend()
256 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_suspend()
266 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(i), in clks_gating_resume()
517 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in ddr_suspend()
519 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in ddr_suspend()
521 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in ddr_suspend()
523 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in ddr_suspend()
534 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(0), in dmc_restore()
536 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(7), in dmc_restore()
538 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(18), in dmc_restore()
540 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(27), in dmc_restore()
561 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20002000); in sram_dbg_uart_suspend()
562 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040004); in sram_dbg_uart_suspend()
568 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(16), 0x20000000); in sram_dbg_uart_resume()
569 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(2), 0x00040000); in sram_dbg_uart_resume()