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Searched refs:CRU_CLKGATES_CON (Results 1 – 9 of 9) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/
H A Dotp.c39 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
41 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
46 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
48 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
53 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(26)); in enable_otp_clk()
55 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in enable_otp_clk()
60 reg = mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(34)); in enable_otp_clk()
62 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(34), in enable_otp_clk()
99 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
104 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(26), in restore_otp_clk()
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/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c52 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
64 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
78 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_disable()
H A Dsoc.h64 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + (i) * 4) macro
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/soc/
H A Dsoc.c149 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_con_save()
157 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
165 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_con_restore()
H A Dsoc.h46 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4)) macro
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.h11 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON0 + (i) * 4) macro
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/soc/
H A Dsoc.c164 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); in soc_sleep_config()
168 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); in soc_sleep_config()
H A Dsoc.h84 #define CRU_CLKGATES_CON(i) (CRU_CLKGATE_CON + ((i) * 4)) macro
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c550 mmio_read_32(CRU_BASE + CRU_CLKGATES_CON(i)); in clk_gate_suspend()
551 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_suspend()
572 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), in clk_gate_resume()