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Searched refs:CPG_PLL0CR (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/renesas/common/include/
H A Drcar_def.h228 #define CPG_PLL0CR (CPG_BASE + 0x00D8U) macro
/rk3399_ARM-atf/plat/renesas/rzg/
H A Dbl2_plat_setup.c938 reg = mmio_read_32(CPG_PLL0CR); in bl2_early_platform_setup2()
940 mmio_write_32(CPG_PLL0CR, reg); in bl2_early_platform_setup2()
/rk3399_ARM-atf/plat/renesas/rcar/
H A Dbl2_plat_setup.c1331 reg = mmio_read_32(CPG_PLL0CR); in bl2_early_platform_setup2()
1333 mmio_write_32(CPG_PLL0CR, reg); in bl2_early_platform_setup2()