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Searched refs:CLKMGR_SDMMC_CLK_ID (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/
H A Dbl2_plat_setup.c177 params.sdmclk = clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID); in bl2_el3_plat_arch_setup()
181 INFO("SDMMC/NAND clock is %u\n", clkmgr_get_rate(CLKMGR_SDMMC_CLK_ID)); in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h271 #define CLKMGR_SDMMC_CLK_ID 11 macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c631 case CLKMGR_SDMMC_CLK_ID: in clkmgr_get_rate()