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Searched refs:CLKMGR_PLLGLOB_DREFCLKDIV (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_clock_manager.h113 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_clock_manager.c122 drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV( in config_clkmgr_handoff()
160 drefclk_div = CLKMGR_PLLGLOB_DREFCLKDIV( in config_clkmgr_handoff()
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h210 #define CLKMGR_PLLGLOB_DREFCLKDIV(x) (((x) & 0x00003000) >> 12) macro