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Searched refs:CLKMGR_PLLGLOB_AREFCLKDIV (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_clock_manager.h112 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000f00) >> 8) macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h209 #define CLKMGR_PLLGLOB_AREFCLKDIV(x) (((x) & 0x00000F00) >> 8) macro
/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_clock_manager.c302 arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob); in get_ref_clk()
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c391 arefclkdiv = CLKMGR_PLLGLOB_AREFCLKDIV(pllglob_val); in get_ref_clk()