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Searched refs:CLKMGR_PERPLL (Results 1 – 5 of 5) sorted by relevance

/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_clock_manager.c134 req_status = mmio_read_32(CLKMGR_PERPLL(MEM)); in pll_source_sync_wait()
146 req_status = mmio_read_32(CLKMGR_PERPLL(MEM)); in pll_source_sync_wait()
171 mmio_write_32(CLKMGR_PERPLL(MEM), val); in pll_source_sync_config()
189 mmio_write_32(CLKMGR_PERPLL(MEM), val); in pll_source_sync_read()
201 *rdata = mmio_read_32(CLKMGR_PERPLL(MEMSTAT)); in pll_source_sync_read()
237 mmio_setbits_32(CLKMGR_PERPLL(BYPASS), CLKMGR_PERPLL_BYPASS_ALL); in config_clkmgr_handoff()
245 mmio_clrbits_32(CLKMGR_PERPLL(PLLGLOB), in config_clkmgr_handoff()
266 mmio_write_32(CLKMGR_PERPLL(PLLGLOB), in config_clkmgr_handoff()
268 mmio_write_32(CLKMGR_PERPLL(FDBCK), hoff_ptr->per_pll_fdbck); in config_clkmgr_handoff()
269 mmio_write_32(CLKMGR_PERPLL(VCOCALIB), perpll_vcocalib); in config_clkmgr_handoff()
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/rk3399_ARM-atf/plat/intel/soc/agilex/soc/
H A Dagilex_clock_manager.c108 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_BYPASS, 0x7f); in config_clkmgr_handoff()
115 mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, in config_clkmgr_handoff()
171 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLGLOB, in config_clkmgr_handoff()
174 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_FDBCK, in config_clkmgr_handoff()
177 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_VCOCALIB, in config_clkmgr_handoff()
181 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC0, in config_clkmgr_handoff()
183 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC1, in config_clkmgr_handoff()
185 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC2, in config_clkmgr_handoff()
187 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLC3, in config_clkmgr_handoff()
189 mmio_write_32(CLKMGR_PERPLL + CLKMGR_PERPLL_PLLM, in config_clkmgr_handoff()
[all …]
H A Dagilex_mmc.c13 mmio_clrbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, in agx_mmc_init()
17 mmio_setbits_32(CLKMGR_PERPLL + CLKMGR_PERPLL_EN, in agx_mmc_init()
/rk3399_ARM-atf/plat/intel/soc/agilex/include/
H A Dagilex_clock_manager.h39 #define CLKMGR_PERPLL 0xffd1007c macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_clock_manager.h90 #define CLKMGR_PERPLL(_reg) (CLKMGR_PERPLL_BASE + \ macro