Searched refs:ARM_SHARED_RAM_BASE (Results 1 – 12 of 12) sorted by relevance
113 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE macro126 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)188 #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE + sizeof(meminfo_t))189 #define ARM_FW_CONFIG_LIMIT (ARM_SHARED_RAM_BASE + \296 ARM_SHARED_RAM_BASE, \
60 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE macro65 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \185 ARM_SHARED_RAM_BASE, \
72 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE83 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8)
201 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && in plat_arm_program_trusted_mailbox()203 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); in plat_arm_program_trusted_mailbox()
29 .mem_base = ARM_SHARED_RAM_BASE,
106 #define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE) macro109 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)264 #define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE
80 zeromem((void *) ARM_SHARED_RAM_BASE, 128); in bl2_platform_setup()
73 ARM_SHARED_RAM_BASE, \
74 ARM_SHARED_RAM_BASE, \
514 #define ARM_SHARED_RAM_BASE (NRD_CSS_BL1_RO_BASE + \ macro523 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \
62 #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE macro76 #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \302 ARM_SHARED_RAM_BASE, \
247 ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \