Searched refs:APU_PLL_BASE (Results 1 – 3 of 3) sorted by relevance
80 #define APU_PLL_BASE (APUSYS_APU_PLL_BASE) macro81 #define APU_PLL4H_PLL1_CON0 (APU_PLL_BASE + 0x008)82 #define APU_PLL4H_PLL1_CON1 (APU_PLL_BASE + 0x00C)83 #define APU_PLL4H_PLL1_CON3 (APU_PLL_BASE + 0x014)85 #define APU_PLL4H_PLL2_CON0 (APU_PLL_BASE + 0x018)86 #define APU_PLL4H_PLL2_CON1 (APU_PLL_BASE + 0x01C)87 #define APU_PLL4H_PLL2_CON3 (APU_PLL_BASE + 0x024)89 #define APU_PLL4H_PLL3_CON0 (APU_PLL_BASE + 0x028)90 #define APU_PLL4H_PLL3_CON1 (APU_PLL_BASE + 0x02C)91 #define APU_PLL4H_PLL3_CON3 (APU_PLL_BASE + 0x034)[all …]
293 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_RST_CON, PLL4H_PLL_HP_SWRSTB); in apu_pll_init()294 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_HP_EN, PLL4H_PLL_HP_EN); in apu_pll_init()295 mmio_setbits_32(APU_PLL_BASE + PLL4HPLL_FHCTL_CLK_CON, PLL4H_PLL_HP_CLKEN); in apu_pll_init()298 mmio_setbits_32(APU_PLL_BASE + pll_hfctl_cfg[pll_idx], (FHCTL0_EN | SFSTR0_EN)); in apu_pll_init()304 mmio_clrsetbits_32(APU_PLL_BASE + pll_con1[pll_idx], in apu_pll_init()307 mmio_write_32(APU_PLL_BASE + pll_fhctl_dds[pll_idx], in apu_pll_init()
67 #define APU_PLL_BASE (APU_PLL) macro