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Searched refs:APU_ACC_CONFG_SET2 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.c32 APU_ACC_CONFG_SET1, APU_ACC_CONFG_SET2,
58 { APU_ACC_CONFG_SET2, BIT(BIT_INVEN_OUT) },
59 { APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU) },
61 { APU_ACC_CONFG_SET2, BIT(BIT_SEL_APU_DIV2) },
228 acc_set1 = APU_ACC_CONFG_SET2; in apupwr_smc_pll_set_rate()
H A Dapupwr_clkctl_def.h160 #define APU_ACC_CONFG_SET2 (APU_ACC_BASE + 0x008) macro
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/
H A Dapusys_power.h132 #define APU_ACC_CONFG_SET2 (0x0008) macro
H A Dapusys_power.c321 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET2, HW_CTRL_EN); in apu_acc_init()