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Searched refs:APU_ACC_CONFG_SET0 (Results 1 – 6 of 6) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.c34 APU_ACC_CONFG_SET0, APU_ACC_CONFG_SET7
49 { APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU) },
51 { APU_ACC_CONFG_SET0, BIT(BIT_SEL_APU_DIV2) },
235 acc_set0 = APU_ACC_CONFG_SET0; in apupwr_smc_pll_set_rate()
H A Dapupwr_clkctl_def.h158 #define APU_ACC_CONFG_SET0 (APU_ACC_BASE + 0x000) macro
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8196/
H A Dapusys_power.h103 #define APU_ACC_CONFG_SET0 (0x000) macro
H A Dapusys_power.c136 apu_w_are(are_idx++, base_reg + APU_ACC_CONFG_SET0, HW_CTRL_EN); in apu_acc_init()
148 apu_w_are(are_idx++, base_reg + APU_ACC_CONFG_SET0, HW_CTRL_EN); in apu_acc_init()
/rk3399_ARM-atf/plat/mediatek/drivers/apusys/mt8188/
H A Dapusys_power.h130 #define APU_ACC_CONFG_SET0 (0x0000) macro
H A Dapusys_power.c315 mmio_write_32(APU_ACC_BASE + APU_ACC_CONFG_SET0, HW_CTRL_EN); in apu_acc_init()