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Searched refs:seccfgr (Results 1 – 5 of 5) sorted by relevance

/optee_os/core/drivers/firewall/
H A Dstm32_risab.c91 uint32_t seccfgr; member
196 _RISAB_PG_SECCFGR_MASK, subr_cfg->seccfgr); in set_block_seccfgr()
381 subr_cfg->seccfgr = _RISAB_PG_SECCFGR_MASK; in parse_risab_rif_conf()
392 subr_cfg->seccfgr = 0; in parse_risab_rif_conf()
615 uint32_t seccfgr = 0; in stm32_risab_check_access() local
649 seccfgr = io_read32(base + _RISAB_PGy_SECCFGR(first_page)); in stm32_risab_check_access()
651 if (!!(q_conf & BIT(RISAB_SEC_SHIFT)) ^ !!(seccfgr & BIT(first_page))) { in stm32_risab_check_access()
748 risab->subr_cfg[i].seccfgr ? "Secure" : "Non secure", in stm32_risab_reconfigure_region()
793 risab->subr_cfg[i].seccfgr = in stm32_risab_pm_suspend()
H A Dstm32_rifsc.c745 uint32_t seccfgr = 0; in stm32_rifsc_check_access() local
767 seccfgr = io_read32(rifsc_base + _RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); in stm32_rifsc_check_access()
773 if (!sec_check && seccfgr & BIT(periph_offset)) in stm32_rifsc_check_access()
800 uint32_t seccfgr = 0; in stm32_rifsc_acquire_access() local
823 seccfgr = io_read32(rifsc_base + _RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); in stm32_rifsc_acquire_access()
824 if (!(seccfgr & BIT(periph_offset))) in stm32_rifsc_acquire_access()
/optee_os/core/drivers/
H A Dstm32_rtc.c297 uint32_t seccfgr = 0; in apply_rif_config() local
330 seccfgr = rtc_dev.conf_data->sec_conf[0]; in apply_rif_config()
333 if (seccfgr == RTC_RIF_FULL_SECURED) { in apply_rif_config()
341 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT, in apply_rif_config()
343 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values; in apply_rif_config()
346 RTC_SECCFGR_MASK & access_mask_reg, seccfgr); in apply_rif_config()
H A Dstm32_gpio.c186 uint32_t seccfgr; member
1122 bank->seccfgr |= gpios_mask; in stm32_gpio_fw_configure()
1124 bank->seccfgr &= ~gpios_mask; in stm32_gpio_fw_configure()
1264 bank->seccfgr = fdt32_to_cpu(*cuint); in dt_stm32_gpio_bank()
1545 bank->seccfgr = io_read32(bank->base + GPIO_SECR_OFFSET); in stm32_gpio_get_conf_sec()
1554 io_write32(bank->base + GPIO_SECR_OFFSET, bank->seccfgr); in stm32_gpio_set_conf_sec()
H A Dstm32_tamp.c697 uint32_t seccfgr = 0; in apply_rif_config() local
740 seccfgr |= _TAMP_SECCFGR_TAMPSEC; in apply_rif_config()
742 seccfgr |= _TAMP_SECCFGR_CNT1SEC; in apply_rif_config()
744 seccfgr |= _TAMP_SECCFGR_CNT2SEC; in apply_rif_config()
755 io_clrsetbits32(base + _TAMP_SECCFGR, access_mask_sec_reg, seccfgr); in apply_rif_config()